Use c_mon_sync_latency to account for sync_reg2 pipeline in dp_bsn_monitor_v2.

libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd

@@ -58,7 +58,9 @@ ARCHITECTURE tb OF tb_dp_bsn_monitor_v2 IS
   CONSTANT c_sync_timeout        : NATURAL := c_frame_len*c_sync_period;
   CONSTANT c_nof_repeat          : NATURAL := g_nof_sync * c_sync_period + 1;
   CONSTANT c_ref_sync_latency    : NATURAL := 7;
-  
+  CONSTANT c_mon_sync_latency    : NATURAL := 1;  -- due to sync_reg2 in dp_bsn_monitor_v2
+  CONSTANT c_exp_sync_latency    : NATURAL := c_ref_sync_latency + c_mon_sync_latency;
+
   -- Error control
   CONSTANT c_skip_sync_nr        : INTEGER := -1;  -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
   CONSTANT c_nof_err             : NATURAL := 2;   -- <= c_sync_period   -- introduce frame errors
@@ -187,7 +189,7 @@ BEGIN
   expected_nof_sop     <= TO_UVEC(            c_sync_period, c_word_w);
   expected_nof_err     <= TO_UVEC(                c_nof_err, c_word_w);
   expected_nof_valid   <= TO_UVEC(c_frame_len*c_sync_period, c_word_w);
-  expected_latency     <= TO_UVEC(       c_ref_sync_latency, c_word_w);
+  expected_latency     <= TO_UVEC(       c_exp_sync_latency, c_word_w);
   
   ------------------------------------------------------------------------------
   -- SISO FLOW CONTROL GENERATION