Fixed rd_data verification for DB buffer read during write conflicts.

applications/apertif/designs/apertif_unb1_fn_beamformer/tb/vhdl/tb_apertif_unb1_fn_beamformer_nodes.vhd

@@ -237,7 +237,7 @@ BEGIN
   
     CONSTANT c_max_X    : NATURAL := 4;
     
-    VARIABLE v_I        : NATURAL;
+    VARIABLE v_I        : INTEGER;
     VARIABLE v_exp_re   : NATURAL;
     VARIABLE v_exp_im   : NATURAL;
     VARIABLE v_exp_data : NATURAL;
@@ -260,10 +260,12 @@ BEGIN
     --       <-> <-> <->                                                 <-> Q_interleave = 2
     FOR u IN 0 TO c_bf.nof_bf_units-1 LOOP
       v_exp_im := u;
-      v_I := 0;
-      FOR bui IN 0 TO N_blk/Q_interleave-1 LOOP
-        FOR t IN 0 TO N_int_x-1 LOOP
-          FOR q IN 0 TO Q_interleave-1 LOOP
+      v_I := c_output_db_nof_words-1;
+      -- Read the DB buffer in reverse order (so with decrementing addresses) to be able to use retry MM read
+      -- after rd_data conflict with firmware write (that uses incrementing addresses)
+      FOR bui IN N_blk/Q_interleave-1 DOWNTO 0 LOOP
+        FOR t IN N_int_x-1 DOWNTO 0 LOOP
+          FOR q IN Q_interleave-1 DOWNTO 0 LOOP
             -- Expected data
             v_exp_re := bui * Q_interleave + q;
             v_exp_data := v_exp_im * 2**c_transport_w + v_exp_re;
@@ -272,13 +274,14 @@ BEGIN
             v_rd_data := TO_UINT(rd_data_db);
             IF v_rd_data/=v_exp_data THEN
               -- Retry MM read when occasionaly MM read and internal firmware write occur at same address and then cause 'X'
+              proc_common_wait_some_cycles(ext_clk, 1);
               mmf_mm_bus_rd(c_mm_file_ram_diag_data_buf_output, u*c_output_db_nof_words_pow2 + v_I, rd_data_db, tb_clk);
               v_rd_data := TO_UINT(rd_data_db);
               nof_rd_data_db_X <= nof_rd_data_db_X + 1;
               REPORT int_to_str(v_I) & int_to_str(nof_rd_data_db_X) & " : " & int_to_str(v_rd_data) & " /= " & int_to_str(v_exp_data);
             END IF;
             ASSERT v_rd_data=v_exp_data REPORT "DB unexpected transpose output data : " & int_to_str(v_rd_data) & " /= " & int_to_str(v_exp_data);
-            v_I := v_I + 1;
+            v_I := v_I - 1;
           END LOOP;
         END LOOP;     
       END LOOP;