Added done to t_mem_ctlr_miso. Added flush to t_mem_ctlr_mosi.

libraries/base/common/src/vhdl/common_mem_pkg.vhd

@@ -51,7 +51,7 @@ PACKAGE common_mem_pkg IS
   
   -- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
   -- Should wider address range or data width be needed, then define a new
-  -- record type eg. t_mem_ddr, t_mem_ctlr or t_mem_bus for that with
+  -- record type eg. t_mem_ctlr or t_mem_bus for that with
   -- sufficient widths.
   
   -- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
@@ -104,7 +104,8 @@ PACKAGE common_mem_pkg IS
   TYPE t_mem_ctlr_miso IS RECORD  
     rddata        : STD_LOGIC_VECTOR(c_mem_ctlr_data_w-1 DOWNTO 0);
     rdval         : STD_LOGIC;
-    waitrequest_n : STD_LOGIC;
+    waitrequest_n : STD_LOGIC;  -- comparable to DP siso.ready
+    done          : STD_LOGIC;  -- comparable to DP siso.xon, not part of Avalon bus, but useful for DDR controller
   END RECORD;
   
   TYPE t_mem_ctlr_mosi IS RECORD  
@@ -114,10 +115,11 @@ PACKAGE common_mem_pkg IS
     rd            : STD_LOGIC;
     burstbegin    : STD_LOGIC;
     burstsize     : STD_LOGIC_VECTOR(c_mem_ctlr_burstsize_w-1 DOWNTO 0);
+    flush         : STD_LOGIC;  -- not part of Avalon bus, but useful for DDR driver
   END RECORD;
   
-  CONSTANT c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((OTHERS=>'0'), '0', '0');
-  CONSTANT c_mem_ctlr_mosi_rst : t_mem_ctlr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'));
+  CONSTANT c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((OTHERS=>'0'), '0', '0', '0');
+  CONSTANT c_mem_ctlr_mosi_rst : t_mem_ctlr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'), '0');
   
   -- Resize functions to fit an integer or an SLV in the corresponding t_mem_ctlr_miso or t_mem_ctlr_mosi field width
   FUNCTION TO_MEM_CTLR_ADDRESS(  n : INTEGER) RETURN STD_LOGIC_VECTOR;  -- unsigned, use integer to support 32 bit range