corrected filenames

boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg

-hdl_lib_name = unb1_test_10GbE
-hdl_library_clause_name = unb1_test_10GbE_lib
+hdl_lib_name = unb1_test_1GbE
+hdl_library_clause_name = unb1_test_1GbE_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
@@ -7,10 +7,10 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    unb1_test_10GbE.vhd
+    unb1_test_1GbE.vhd
     
 test_bench_files = 
-    tb_unb1_test_10GbE.vhd
+    tb_unb1_test_1GbE.vhd
 
 synth_top_level_entity =
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg

-hdl_lib_name = unb1_test_10GbE
-hdl_library_clause_name = unb1_test_10GbE_lib
+hdl_lib_name = unb1_test_all
+hdl_library_clause_name = unb1_test_all_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
@@ -7,10 +7,10 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    unb1_test_10GbE.vhd
+    unb1_test_all.vhd
     
 test_bench_files = 
-    tb_unb1_test_10GbE.vhd
+    tb_unb1_test_all.vhd
 
 synth_top_level_entity =
 

boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg

-hdl_lib_name = unb1_test_10GbE
-hdl_library_clause_name = unb1_test_10GbE_lib
+hdl_lib_name = unb1_test_ddr
+hdl_library_clause_name = unb1_test_ddr_lib
 hdl_lib_uses_synth = unb1_board unb1_test
 hdl_lib_uses_sim = 
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g_single_rank_800_master ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
@@ -7,10 +7,10 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_uphy_4g
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
-    unb1_test_10GbE.vhd
+    unb1_test_ddr.vhd
     
 test_bench_files = 
-    tb_unb1_test_10GbE.vhd
+    tb_unb1_test_ddr.vhd
 
 synth_top_level_entity =