New unb2b_minimal design to use with E1SG version of UniBoard2

boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg

+hdl_lib_name = unb2b_minimal
+hdl_library_clause_name = unb2b_minimal_lib
+hdl_lib_uses_synth = common technology mm unb2b_board 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    src/vhdl/qsys_unb2b_minimal_pkg.vhd
+    src/vhdl/mmm_unb2b_minimal.vhd
+    src/vhdl/unb2b_minimal.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_unb2b_minimal.vhd
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    #quartus/qsys_unb2b_minimal.qsys .
+    quartus .
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2b_minimal_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+