Fixed regression tests

libraries/base/common/hdllib.cfg

@@ -227,7 +227,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_common_fanout_tree.vhd
     tb/vhdl/tb_tb_common_multiplexer.vhd
     tb/vhdl/tb_tb_common_operation_tree.vhd
-    #tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd  -- fails for unb2c
+    tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd 
     tb/vhdl/tb_tb_common_reorder_symbol.vhd
     tb/vhdl/tb_tb_common_rl.vhd
     tb/vhdl/tb_tb_common_rl_register.vhd

libraries/base/reorder/hdllib.cfg

@@ -42,7 +42,7 @@ test_bench_files =
 
 regression_test_vhdl = 
     tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd   
-#    tb/vhdl/tb_tb_reorder_col.vhd    -- fails in unb2c
+    tb/vhdl/tb_tb_reorder_col.vhd 
 
 
 [modelsim_project_file]

libraries/base/ss/hdllib.cfg

@@ -20,7 +20,7 @@ test_bench_files =
     tb/vhdl/tb_tb_ss.vhd
 
 regression_test_vhdl = 
-#    tb/vhdl/tb_tb_ss.vhd  -- fails in unb2c
+    tb/vhdl/tb_tb_ss.vhd
 
 
 [modelsim_project_file]

libraries/io/tr_10GbE/hdllib.cfg

@@ -14,7 +14,7 @@ test_bench_files =
     tb/vhdl/tb_tb_tr_10GbE.vhd
 
 regression_test_vhdl = 
-#    tb/vhdl/tb_tb_tr_10GbE.vhd -- fails in unb2c
+    tb/vhdl/tb_tb_tr_10GbE.vhd
 
 
 [modelsim_project_file]

libraries/technology/eth_10g/hdllib.cfg

@@ -26,7 +26,7 @@ test_bench_files =
     tb_tb_tech_eth_10g.vhd
     
 regression_test_vhdl = 
-#    tb_tb_tech_eth_10g.vhd -- fails in unb2c
+    tb_tb_tech_eth_10g.vhd
 
 [modelsim_project_file]
 

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd

@@ -71,6 +71,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
           outdata_aclr_b  : string;
           outdata_reg_b  : string;
           power_up_uninitialized  : string;
+          read_during_write_mode_mixed_ports : string;
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -116,6 +117,7 @@ BEGIN
             outdata_aclr_b  => "NONE",
             outdata_reg_b  => c_outdata_reg_b,
             power_up_uninitialized  => "FALSE",
+            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,

libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd

@@ -80,6 +80,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crw_crw IS
           power_up_uninitialized  : string;
           read_during_write_mode_port_a  : string;
           read_during_write_mode_port_b  : string;
+          read_during_write_mode_mixed_ports : string;
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -137,6 +138,7 @@ BEGIN
             power_up_uninitialized  => "FALSE",
             read_during_write_mode_port_a  => "NEW_DATA_NO_NBE_READ",
             read_during_write_mode_port_b  => "NEW_DATA_NO_NBE_READ",
+            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,