Apply 10% marging to g_sync_timeout in mms_dp_bsn_monitor.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -41,7 +41,7 @@ ENTITY node_sdp_adc_input_and_timing IS
   GENERIC (
     g_technology              : NATURAL := c_tech_select_default;
     g_buf_nof_data            : NATURAL := c_sdp_V_si_db;
-    g_bsn_nof_clk_per_sync    : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
+    g_bsn_nof_clk_per_sync    : NATURAL := c_sdp_N_clk_per_sync;  -- Default 200M, overide for short simulation
     g_sim                     : BOOLEAN := FALSE  
   );
   PORT (
@@ -119,8 +119,9 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
   CONSTANT c_wg_buf_addr_w          : NATURAL := 10; --default value of WG for 1024 samples;
   SIGNAL trigger_wg                 : STD_LOGIC;
 
-  -- Frame parameters TBC
-  CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
+  -- Frame parameters
+  CONSTANT c_bs_sync_timeout        : NATURAL := (g_bsn_nof_clk_per_sync * 11) / 10;  -- +10% margin
+  CONSTANT c_bs_bsn_w               : NATURAL := 64; -- > 51;
   CONSTANT c_bs_block_size          : NATURAL := c_sdp_N_fft; -- =1024;
   CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
 
@@ -375,7 +376,7 @@ BEGIN
   u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
   GENERIC MAP (
     g_nof_streams        => 1,  -- They're all the same
-    g_sync_timeout       => g_bsn_nof_clk_per_sync,
+    g_sync_timeout       => c_bs_sync_timeout,
     g_bsn_w              => c_bs_bsn_w,
     g_log_first_bsn      => FALSE
   )