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RTSD
HDL
Commits
1deaba58
Commit
1deaba58
authored
May 28, 2015
by
Pepping
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Added methods and classes
parent
6240452f
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Changes
1
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1 changed file
tools/oneclick/base/entity.py
+91
-13
91 additions, 13 deletions
tools/oneclick/base/entity.py
with
91 additions
and
13 deletions
tools/oneclick/base/entity.py
+
91
−
13
View file @
1deaba58
...
...
@@ -57,14 +57,26 @@ class Generic:
self
.
type
=
type
self
.
default
=
default
def
setPortDir
(
self
,
newDir
):
self
.
dir
=
newDir
class
Constant
:
def
__init__
(
self
,
name
,
type
,
value
=
""
):
self
.
name
=
name
self
.
type
=
type
self
.
value
=
value
class
signal
:
def
__init__
(
self
,
name
,
type
,
default
=
""
):
self
.
name
=
name
self
.
type
=
type
self
.
default
=
default
class
Entity
:
s_port_start
=
"
PORT (
\n
"
s_port_map_start
=
"
PORT MAP(
\n
"
s_generic_start
=
"
GENERIC (
\n
"
s_generic_map_start
=
"
GENERIC MAP(
\n
"
def
__init__
(
self
,
name
=
""
):
"""
...
...
@@ -81,7 +93,9 @@ class Entity:
self
.
longestGenericType
=
8
def
read_entity_from_file
(
self
,
path
,
name
):
f
=
file
((
path
+
name
+
"
.vhd
"
),
"
r
"
)
fname
=
path
+
name
+
"
.vhd
"
if
not
(
os
.
path
.
isfile
(
fname
)):
sys
.
exit
(
'
Error : Specified VHD file does not exist:
'
+
fname
)
f
=
file
(
fname
,
"
r
"
)
s
=
""
s
=
f
.
readline
()
# Read the entity name
...
...
@@ -146,7 +160,45 @@ class Entity:
s
=
s
[
0
:
i
]
+
"
\n
"
return
s
.
strip
()
def
make_instance
(
self
,
inst_type
=
"
ENTITY
"
):
def
make_instantiation
(
self
,
connect
=
True
):
if
self
.
generics
:
self
.
set_longest_generic_name
()
self
.
set_longest_generic_type
()
if
self
.
ports
:
self
.
set_longest_port_name
()
self
.
set_longest_port_dir
()
# Create start
s_return
=
"
u_inst_
"
+
self
.
name
+
"
: ENTITY work.
"
+
self
.
name
+
"
\n
"
for
i
in
range
(
len
(
self
.
generics
)):
if
(
i
==
0
):
s_return
=
s_return
+
self
.
s_generic_map_start
s_generic
=
"
"
+
self
.
generics
[
i
].
name
.
ljust
(
self
.
longestGenericName
)
+
"
=>
"
if
(
connect
):
s_generic
=
s_generic
+
self
.
generics
[
i
].
name
if
(
i
!=
len
(
self
.
generics
)
-
1
):
s_generic
=
s_generic
+
"
,
\n
"
else
:
s_generic
=
s_generic
+
"
\n
)
\n
"
s_return
=
s_return
+
s_generic
for
i
in
range
(
len
(
self
.
ports
)):
if
(
i
==
0
):
s_return
=
s_return
+
self
.
s_port_map_start
s_port
=
"
"
+
self
.
ports
[
i
].
name
.
ljust
(
self
.
longestPortName
)
+
"
=>
"
if
(
connect
):
s_port
=
s_port
+
self
.
ports
[
i
].
name
if
(
i
!=
len
(
self
.
ports
)
-
1
):
s_port
=
s_port
+
"
,
\n
"
else
:
s_port
=
s_port
+
"
\n
);
\n
"
s_return
=
s_return
+
s_port
return
s_return
def
make_definition
(
self
,
inst_type
=
"
ENTITY
"
):
if
self
.
generics
:
self
.
set_longest_generic_name
()
...
...
@@ -185,11 +237,11 @@ class Entity:
return
s_return
def
make_entity_
instance
(
self
,
indend
=
0
):
return
self
.
apply_indend
(
self
.
make_
instance
(
"
ENTITY
"
),
indend
)
def
make_entity_
definition
(
self
,
indend
=
0
):
return
self
.
apply_indend
(
self
.
make_
definition
(
"
ENTITY
"
),
indend
)
def
make_component_
instance
(
self
,
indend
=
0
):
return
self
.
apply_indend
(
self
.
make_
instance
(
"
COMPONENT
"
),
indend
)
def
make_component_
definition
(
self
,
indend
=
0
):
return
self
.
apply_indend
(
self
.
make_
definition
(
"
COMPONENT
"
),
indend
)
def
apply_indend
(
self
,
s
,
indend
):
s_indend
=
""
...
...
@@ -198,6 +250,10 @@ class Entity:
s_return
=
s_indend
+
s
.
replace
(
'
\n
'
,
'
\n
'
+
s_indend
)
return
(
s_return
)
def
comment
(
self
,
s
):
s_return
=
"
--
"
+
s
.
replace
(
'
\n
'
,
'
\n
'
+
"
--
"
)
+
'
\n
'
return
(
s_return
)
def
set_longest_port_name
(
self
):
self
.
portNames
=
[]
for
i
in
range
(
len
(
self
.
ports
)):
...
...
@@ -226,3 +282,25 @@ class Entity:
newPort
=
Port
(
name
,
dir
,
type
,
default
)
self
.
ports
.
append
(
newPort
)
def
add_generic
(
self
,
name
,
type
,
default
=
""
):
newGeneric
=
Generic
(
name
,
type
,
default
)
self
.
generics
.
append
(
newGeneric
)
def
replace_std_logic_vector_with_std_logic
(
self
):
for
i
in
self
.
ports
:
if
i
.
type
==
"
std_logic_vector(0 downto 0)
"
:
i
.
type
=
"
std_logic
"
elif
i
.
type
==
"
STD_LOGIC_VECTOR(0 DOWNTO 0)
"
:
i
.
type
=
"
STD_LOGIC
"
class
Architecture
:
def
__init__
(
self
,
name
=
""
):
"""
"""
self
.
name
=
name
self
.
constants
=
[]
self
.
signals
=
[]
self
.
components
=
[]
\ No newline at end of file
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