Small comment cleans.

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -131,7 +131,7 @@ architecture str of ip_arria10_e1sg_jesd204b is
   signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_rx_somf_arr       : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
 
-  -- output to control ADC initialization / syncronization phase
+  -- outputs to control ADC initialization/syncronization phase
   signal jesd204b_sync_n_internal_arr   : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_sync_n_enabled_arr    : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_sync_n_combined_arr   : std_logic_vector(g_nof_sync_n - 1 downto 0);
@@ -383,7 +383,7 @@ begin
         dout => mm_rx_xcvr_ready_in_arr(i)
       );
 
-      -- Invert thr active-low resets
+      -- Invert the active-low resets
       rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
       rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
       rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
@@ -496,8 +496,8 @@ begin
     u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
     port map (
       clock                        => rxlink_clk,
-      reset                        => xcvr_rst_arr(0),  -- From Reset Sequencer output1 as per example design, the
-                                                        -- reset input is synchronised internally.
+      reset                        => xcvr_rst_arr(0),  -- From Reset Sequencer output1 as per example design,
+                                                        -- the reset input is synchronised internally.
       rx_analogreset               => rx_analogreset_arr,  -- output to reset RX PMA. Release before deasserting
                                                            -- link and avs resets (Intel JESD204B-UG p70)
       rx_cal_busy                  => rx_cal_busy_arr,  -- input from PHY

libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd

@@ -131,7 +131,7 @@ architecture str of ip_arria10_e2sg_jesd204b is
   signal jesd204b_rx_link_valid_arr : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_rx_somf_arr       : std_logic_vector(c_jesd204b_rx_somf_w * g_nof_streams - 1 downto 0);
 
-  -- output to control ADC initialization / syncronization phase
+  -- outputs to control ADC initialization/syncronization phase
   signal jesd204b_sync_n_internal_arr   : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_sync_n_enabled_arr    : std_logic_vector(g_nof_streams - 1 downto 0);
   signal jesd204b_sync_n_combined_arr   : std_logic_vector(g_nof_sync_n - 1 downto 0);
@@ -383,7 +383,7 @@ begin
         dout => mm_rx_xcvr_ready_in_arr(i)
       );
 
-      -- Invert thr active-low resets
+      -- Invert the active-low resets
       rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
       rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
       rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
@@ -496,8 +496,8 @@ begin
     u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
     port map (
       clock                        => rxlink_clk,
-      reset                        => xcvr_rst_arr(0),  -- From Reset Sequencer output1 as per example design, the
-                                                        -- reset input is synchronised internally.
+      reset                        => xcvr_rst_arr(0),  -- From Reset Sequencer output1 as per example design,
+                                                        -- the reset input is synchronised internally.
       rx_analogreset               => rx_analogreset_arr,  -- output to reset RX PMA. Release before deasserting
                                                            -- link and avs resets (Intel JESD204B-UG p70)
       rx_cal_busy                  => rx_cal_busy_arr,  -- input from PHY