Added dp_pipeline_arr.vhd

libraries/base/dp/hdllib.cfg

@@ -25,6 +25,7 @@ synth_files =
     $UNB/Firmware/modules/dp/src/vhdl/dp_hold_ctrl.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_hold_input.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_pipeline.vhd
+    src/vhdl/dp_pipeline_arr.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_pipeline_ready.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
     $UNB/Firmware/modules/dp/src/vhdl/dp_packet_detect.vhd

libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.all;
+USE work.dp_stream_pkg.ALL;
+
+-- Purpose:
+--   Pipeline array of g_nof_streams by g_pipeline cycles.
+-- Description:
+--   See dp_pipeline.
+
+ENTITY dp_pipeline_arr IS
+  GENERIC (
+    g_nof_streams : NATURAL := 1;
+    g_pipeline    : NATURAL := 1  -- 0 for wires, > 0 for registers, 
+  );
+  PORT (
+    rst          : IN  STD_LOGIC;
+    clk          : IN  STD_LOGIC;
+    -- ST sink
+    snk_out_arr  : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
+    snk_in_arr   : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    -- ST source
+    src_in_arr   : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+    src_out_arr  : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+  );
+END dp_pipeline_arr;
+
+
+ARCHITECTURE str OF dp_pipeline_arr IS
+
+BEGIN
+
+  gen_nof_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_p : ENTITY work.dp_pipeline
+    GENERIC MAP (
+      g_pipeline => g_pipeline
+    )
+    PORT MAP (
+      rst          => rst,
+      clk          => clk,
+      -- ST sink
+      snk_out      => snk_out_arr(I),
+      snk_in       => snk_in_arr(I),
+      -- ST source
+      src_in       => src_in_arr(I),
+      src_out      => src_out_arr(I)
+    );
+  END GENERATE;
+  
+END str;