repaired bug in cfg files unb1

boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg

@@ -26,7 +26,7 @@ synth_top_level_entity =
 quartus_copy_files = 
     quartus/sopc_unb1_bn_terminal_bg.sopc .
     $RADIOHDL_WORK/libraries/base/diag/src/data data 
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 quartus_qsf_files = 
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -28,7 +28,7 @@ synth_top_level_entity =
 
 quartus_copy_files =
     quartus/sopc_unb1_ddr3.sopc .
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

@@ -28,7 +28,7 @@ synth_top_level_entity =
 
 quartus_copy_files =
     quartus/sopc_unb_ddr3_transpose.sopc .
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg

@@ -24,7 +24,7 @@ synth_top_level_entity =
 
 quartus_copy_files = 
     quartus/sopc_unb1_fn_terminal_db.sopc .
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 quartus_qsf_files =                                                       
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

boards/uniboard1/designs/unb1_heater/hdllib.cfg

@@ -24,7 +24,7 @@ synth_top_level_entity =
 
 quartus_copy_files =
     quartus/qsys_unb1_heater.qsys .
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf

boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg

 hdl_lib_name = unb1_terminal_bg_mesh_db
 hdl_library_clause_name = unb1_terminal_bg_mesh_db_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse
-hdl_lib_uses_sim = 
+hdl_lib_uses_sim =
 hdl_lib_technology = ip_stratixiv
 
-synth_files =   
+synth_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
     src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
     src/vhdl/unb1_terminal_bg_mesh_db.vhd
-    
-test_bench_files = 
+
+test_bench_files =
     tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
 
 
 [modelsim_project_file]
-modelsim_copy_files = 
-    src/hex hex                                                   
+modelsim_copy_files =
+    src/hex hex
     $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
 
@@ -24,17 +24,17 @@ modelsim_copy_files =
 [quartus_project_file]
 synth_top_level_entity =
 
-quartus_copy_files = 
+quartus_copy_files =
     quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
-    src/hex hex                                                   
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    src/hex hex
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 
-quartus_qsf_files = 
+quartus_qsf_files =
     $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_terminal_bg_mesh_db_pins.tcl
-    
+
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
 

boards/uniboard1/designs/unb1_test/hdllib.cfg

@@ -22,5 +22,5 @@ modelsim_copy_files =
 
 [quartus_project_file]
 quartus_copy_files = 
-   $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+   $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
 

boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg

@@ -25,7 +25,7 @@ modelsim_copy_files =
 synth_top_level_entity =
 
 quartus_copy_files =
-    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl ${RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
     quartus/qsys_unb1_tr_10GbE.qsys .
 #    src/hex/ hex