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Commit 1bb1dd6a authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added MM register and bus for the filter coefficients.

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applications/apertif_unb1_correlator/quartus/qsys_apertif_unb1_correlator.qsys
+ 122
− 48
View file @ 1bb1dd6a
...@@ -52,14 +52,6 @@ ...@@ -52,14 +52,6 @@
type = "int"; type = "int";
} }
} }
element c0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element altpll_0.c0 element altpll_0.c0
{ {
datum _clockDomain datum _clockDomain
...@@ -68,6 +60,14 @@ ...@@ -68,6 +60,14 @@
type = "String"; type = "String";
} }
} }
element c0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element altpll_0.c1 element altpll_0.c1
{ {
datum _clockDomain datum _clockDomain
...@@ -104,7 +104,7 @@ ...@@ -104,7 +104,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "14336"; value = "24576";
type = "long"; type = "long";
} }
} }
...@@ -129,19 +129,24 @@ ...@@ -129,19 +129,24 @@
type = "long"; type = "long";
} }
} }
element pio_pps.mem element ram_fil_coefs.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "328"; value = "14336";
type = "long"; type = "long";
} }
} }
element reg_diag_data_buf.mem element reg_wdi.mem
{ {
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "336"; value = "12288";
type = "long"; type = "long";
} }
} }
...@@ -158,20 +163,23 @@ ...@@ -158,20 +163,23 @@
type = "long"; type = "long";
} }
} }
element rom_system_info.mem element reg_diag_data_buf.mem
{ {
datum _lockedAddress datum baseAddress
{ {
value = "1"; value = "336";
type = "boolean"; type = "long";
}
} }
element reg_unb_sens.mem
{
datum baseAddress datum baseAddress
{ {
value = "4096"; value = "224";
type = "long"; type = "long";
} }
} }
element reg_wdi.mem element rom_system_info.mem
{ {
datum _lockedAddress datum _lockedAddress
{ {
...@@ -180,15 +188,15 @@ ...@@ -180,15 +188,15 @@
} }
datum baseAddress datum baseAddress
{ {
value = "12288"; value = "4096";
type = "long"; type = "long";
} }
} }
element reg_unb_sens.mem element pio_pps.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "224"; value = "328";
type = "long"; type = "long";
} }
} }
...@@ -266,14 +274,6 @@ ...@@ -266,14 +274,6 @@
type = "String"; type = "String";
} }
} }
element altpll_1.pll_slave
{
datum baseAddress
{
value = "304";
type = "long";
}
}
element altpll_0.pll_slave element altpll_0.pll_slave
{ {
datum _lockedAddress datum _lockedAddress
...@@ -287,6 +287,14 @@ ...@@ -287,6 +287,14 @@
type = "long"; type = "long";
} }
} }
element altpll_1.pll_slave
{
datum baseAddress
{
value = "304";
type = "long";
}
}
element ram_diag_data_buf element ram_diag_data_buf
{ {
datum _sortIndex datum _sortIndex
...@@ -295,6 +303,14 @@ ...@@ -295,6 +303,14 @@
type = "int"; type = "int";
} }
} }
element ram_fil_coefs
{
datum _sortIndex
{
value = "19";
type = "int";
}
}
element reg_diag_data_buf.read element reg_diag_data_buf.read
{ {
datum _tags datum _tags
...@@ -335,27 +351,19 @@ ...@@ -335,27 +351,19 @@
type = "int"; type = "int";
} }
} }
element pio_wdi.s1 element pio_debug_wave.s1
{
datum baseAddress
{
value = "288";
type = "long";
}
}
element timer_0.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "192"; value = "272";
type = "long"; type = "long";
} }
} }
element pio_debug_wave.s1 element pio_wdi.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "272"; value = "288";
type = "long"; type = "long";
} }
} }
...@@ -372,6 +380,14 @@ ...@@ -372,6 +380,14 @@
type = "long"; type = "long";
} }
} }
element timer_0.s1
{
datum baseAddress
{
value = "192";
type = "long";
}
}
element timer_0 element timer_0
{ {
datum _sortIndex datum _sortIndex
...@@ -400,10 +416,10 @@ ...@@ -400,10 +416,10 @@
<parameter name="globalResetBus" value="false" /> <parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VHDL" /> <parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" /> <parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName" value="apertif_unb1_correlator.qpf" /> <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" /> <parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" /> <parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1418396167104" /> <parameter name="timeStamp" value="1418978186377" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript> <instanceScript></instanceScript>
<interface <interface
...@@ -1003,6 +1019,41 @@ ...@@ -1003,6 +1019,41 @@
dir="end" /> dir="end" />
<interface name="altpll_1_c0" internal="altpll_1.c0" type="clock" dir="start" /> <interface name="altpll_1_c0" internal="altpll_1.c0" type="clock" dir="start" />
<interface name="reset" internal="CLK.clk_in_reset" type="reset" dir="end" /> <interface name="reset" internal="CLK.clk_in_reset" type="reset" dir="end" />
<interface
name="ram_fil_coefs_reset"
internal="ram_fil_coefs.reset"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_clk"
internal="ram_fil_coefs.clk"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_address"
internal="ram_fil_coefs.address"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_write"
internal="ram_fil_coefs.write"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_writedata"
internal="ram_fil_coefs.writedata"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_read"
internal="ram_fil_coefs.read"
type="conduit"
dir="end" />
<interface
name="ram_fil_coefs_readdata"
internal="ram_fil_coefs.readdata"
type="conduit"
dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0"> <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" /> <parameter name="clockFrequency" value="25000000" />
<parameter name="clockFrequencyKnown" value="true" /> <parameter name="clockFrequencyKnown" value="true" />
...@@ -1379,8 +1430,8 @@ q]]></parameter> ...@@ -1379,8 +1430,8 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='altpll_1.pll_slave' start='0x130' end='0x140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x140' end='0x148' /><slave name='pio_pps.mem' start='0x148' end='0x150' /><slave name='reg_diag_data_buf.mem' start='0x150' end='0x158' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='altpll_0.pll_slave' start='0x100' end='0x110' /><slave name='pio_debug_wave.s1' start='0x110' end='0x120' /><slave name='pio_wdi.s1' start='0x120' end='0x130' /><slave name='altpll_1.pll_slave' start='0x130' end='0x140' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x140' end='0x148' /><slave name='pio_pps.mem' start='0x148' end='0x150' /><slave name='reg_diag_data_buf.mem' start='0x150' end='0x158' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='ram_fil_coefs.mem' start='0x3800' end='0x4000' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' /><slave name='ram_diag_data_buf.mem' start='0x5000' end='0x6000' /><slave name='cpu_0.jtag_debug_module' start='0x6000' end='0x6800' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" /> <parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Stratix IV" /> <parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" /> <parameter name="internalIrqMaskSystemInfo" value="7" />
...@@ -1591,13 +1642,18 @@ q]]></parameter> ...@@ -1591,13 +1642,18 @@ q]]></parameter>
<parameter name="inputClockFrequency" value="0" /> <parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" /> <parameter name="resetSynchronousEdges" value="NONE" />
</module> </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_fil_coefs">
<parameter name="g_adr_w" value="9" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
<connection <connection
kind="avalon" kind="avalon"
version="11.1" version="11.1"
start="cpu_0.instruction_master" start="cpu_0.instruction_master"
end="cpu_0.jtag_debug_module"> end="cpu_0.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" /> <parameter name="baseAddress" value="0x6000" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -1605,7 +1661,7 @@ q]]></parameter> ...@@ -1605,7 +1661,7 @@ q]]></parameter>
start="cpu_0.data_master" start="cpu_0.data_master"
end="cpu_0.jtag_debug_module"> end="cpu_0.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" /> <parameter name="baseAddress" value="0x6000" />
</connection> </connection>
<connection <connection
kind="avalon" kind="avalon"
...@@ -1966,4 +2022,22 @@ q]]></parameter> ...@@ -1966,4 +2022,22 @@ q]]></parameter>
version="11.1" version="11.1"
start="CLK.clk" start="CLK.clk"
end="altpll_1.inclk_interface" /> end="altpll_1.inclk_interface" />
<connection
kind="clock"
version="11.1"
start="altpll_0.c0"
end="ram_fil_coefs.system" />
<connection
kind="reset"
version="11.1"
start="cpu_0.jtag_debug_module_reset"
end="ram_fil_coefs.system_reset" />
<connection
kind="avalon"
version="11.1"
start="cpu_0.data_master"
end="ram_fil_coefs.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3800" />
</connection>
</system> </system>
applications/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+ 11
− 3
View file @ 1bb1dd6a
...@@ -177,6 +177,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS ...@@ -177,6 +177,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL correlator_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0); SIGNAL correlator_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0); SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi; SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso; SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi; SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
...@@ -225,8 +228,8 @@ BEGIN ...@@ -225,8 +228,8 @@ BEGIN
dp_clk => dp_clk, dp_clk => dp_clk,
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
ram_fil_coefs_mosi => c_mem_mosi_rst, ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => OPEN, ram_fil_coefs_miso => ram_fil_coefs_miso,
ram_st_sst_mosi => c_mem_mosi_rst, ram_st_sst_mosi => c_mem_mosi_rst,
ram_st_sst_miso => OPEN, ram_st_sst_miso => OPEN,
reg_bg_ctrl_mosi => c_mem_mosi_rst, reg_bg_ctrl_mosi => c_mem_mosi_rst,
...@@ -379,7 +382,8 @@ BEGIN ...@@ -379,7 +382,8 @@ BEGIN
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim, g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr, g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr g_sim_node_nr => g_sim_node_nr,
g_wpfb => c_wpfb
) )
PORT MAP( PORT MAP(
xo_clk => xo_clk, xo_clk => xo_clk,
...@@ -422,6 +426,10 @@ BEGIN ...@@ -422,6 +426,10 @@ BEGIN
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi, ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso, ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-- Filter coefficients
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
-- eth1g -- eth1g
eth1g_tse_clk => eth1g_tse_clk, eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst, eth1g_mm_rst => eth1g_mm_rst,
......
applications/apertif_unb1_correlator/src/vhdl/mmm_apertif_unb1_correlator.vhd
+ 28
− 2
View file @ 1bb1dd6a
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib; LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, wpfb_lib;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
...@@ -28,12 +28,14 @@ USE unb1_board_lib.unb1_board_pkg.ALL; ...@@ -28,12 +28,14 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL; USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL; USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL; USE mm_lib.mm_file_unb_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
ENTITY mmm_apertif_unb1_correlator IS ENTITY mmm_apertif_unb1_correlator IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0 g_sim_node_nr : NATURAL := 0;
g_wpfb : t_wpfb
); );
PORT ( PORT (
xo_clk : IN STD_LOGIC; xo_clk : IN STD_LOGIC;
...@@ -70,6 +72,10 @@ ENTITY mmm_apertif_unb1_correlator IS ...@@ -70,6 +72,10 @@ ENTITY mmm_apertif_unb1_correlator IS
ram_diag_data_buf_mosi : OUT t_mem_mosi; ram_diag_data_buf_mosi : OUT t_mem_mosi;
ram_diag_data_buf_miso : IN t_mem_miso; ram_diag_data_buf_miso : IN t_mem_miso;
-- Filter coefficients
ram_fil_coefs_mosi : OUT t_mem_mosi;
ram_fil_coefs_miso : IN t_mem_miso;
-- eth1g -- eth1g
eth1g_tse_clk : OUT STD_LOGIC; eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC; eth1g_mm_rst : OUT STD_LOGIC;
...@@ -92,6 +98,9 @@ END mmm_apertif_unb1_correlator; ...@@ -92,6 +98,9 @@ END mmm_apertif_unb1_correlator;
ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
-- ( 64 * 8 / 1 )
CONSTANT c_ram_fil_coefs_addr_w : natural := ceil_log2(g_wpfb.nof_points * g_wpfb.nof_taps / g_wpfb.wb_factor);
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz CONSTANT c_mm_clk_period : TIME := 8 ns; -- 125 MHz
CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN"); CONSTANT c_sim_node_type : STRING(1 TO 2):= sel_a_b(g_sim_node_nr<4, "FN", "BN");
...@@ -202,6 +211,15 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS ...@@ -202,6 +211,15 @@ ARCHITECTURE str OF mmm_apertif_unb1_correlator IS
reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export reg_diag_data_buf_address_export : out std_logic_vector(9 downto 0); -- export
reg_diag_data_buf_clk_export : out std_logic; -- export reg_diag_data_buf_clk_export : out std_logic; -- export
reg_diag_data_buf_reset_export : out std_logic; -- export reg_diag_data_buf_reset_export : out std_logic; -- export
ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_fil_coefs_read_export : out std_logic; -- export
ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_fil_coefs_write_export : out std_logic; -- export
ram_fil_coefs_address_export : out std_logic_vector(8 downto 0); -- export
ram_fil_coefs_clk_export : out std_logic; -- export
ram_fil_coefs_reset_export : out std_logic; -- export
clk_clk : in std_logic; clk_clk : in std_logic;
reset_reset_n : in std_logic; reset_reset_n : in std_logic;
altpll_1_c0_clk : out std_logic; altpll_1_c0_clk : out std_logic;
...@@ -354,6 +372,14 @@ BEGIN ...@@ -354,6 +372,14 @@ BEGIN
reg_diag_data_buf_clk_export => OPEN, reg_diag_data_buf_clk_export => OPEN,
reg_diag_data_buf_reset_export => OPEN, reg_diag_data_buf_reset_export => OPEN,
ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_ram_fil_coefs_addr_w-1 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
clk_clk => clk_clk, clk_clk => clk_clk,
reset_reset_n => clk_clk_in_reset_reset_n, reset_reset_n => clk_clk_in_reset_reset_n,
altpll_1_c0_clk => altpll_1_c0_clk, altpll_1_c0_clk => altpll_1_c0_clk,
......
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