Added tb_tb_dp_fifo_fill_eop

libraries/base/dp/hdllib.cfg

@@ -263,6 +263,7 @@ test_bench_files =
     tb/vhdl/tb_tb_dp_fifo_sc.vhd
     tb/vhdl/tb_tb_dp_fifo_fill.vhd
     tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
+    tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
     tb/vhdl/tb_tb_dp_fifo_dc.vhd
     tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
     tb/vhdl/tb_tb_dp_frame_scheduler.vhd
@@ -318,6 +319,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd  
     tb/vhdl/tb_tb_dp_fifo_fill.vhd
     tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
+    tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
     tb/vhdl/tb_tb_dp_fifo_info.vhd
     tb/vhdl/tb_tb_dp_fifo_sc.vhd
     tb/vhdl/tb_tb_dp_flush.vhd

libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd

@@ -132,7 +132,7 @@ ARCHITECTURE tb OF tb_dp_fifo_fill_eop IS
   SIGNAL out_val        : STD_LOGIC;
   SIGNAL out_sop        : STD_LOGIC;
   SIGNAL out_eop        : STD_LOGIC;
-  SIGNAL prev_out_data  : STD_LOGIC_VECTOR(out_data'RANGE);
+  SIGNAL prev_out_data  : STD_LOGIC_VECTOR(out_data'RANGE) := (OTHERS=>'0');
   
   SIGNAL state          : t_dp_state_enum;
   

libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+
+-- Purpose:
+--   Multi test bench for dp_fifo_fill_eop
+-- Description:
+--   Runs two tb_dp_fifo_fill_eop testbenches, one for single clock and one for
+--   dual clock.
+-- Remark:
+-- Usage:
+-- > as 10
+-- > run -all
+-- . signal tb_end will stop the simulation by stopping the clk
+-- . the tb is self checking
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_tb_dp_fifo_fill_eop IS
+END tb_tb_dp_fifo_fill_eop;
+
+
+ARCHITECTURE tb OF tb_tb_dp_fifo_fill_eop IS
+  SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+  -- Try FIFO settings : GENERIC MAP (g_dut_use_dual_clock, g_dut_use_bsn, g_dut_use_empty, g_dut_use_channel, g_dut_use_sync, g_dut_fifo_rl, g_dut_fifo_size, g_dut_fifo_fill, g_dut_use_rd_fill_32b)
+  u_dut_sc          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => FALSE); 
+  u_dut_dc          : ENTITY work.tb_dp_fifo_fill_eop GENERIC MAP (g_dut_use_dual_clock => TRUE);
+  
+END tb;