-Added feauture for inverted clock for qsys.

tools/oneclick/base/mmm_gen.py

@@ -80,8 +80,7 @@ USE tech_tse_lib.tb_tech_tse_pkg.ALL;\n\n"
 s_signals_clk = "SIGNAL i_mm_clk   : STD_LOGIC := '1';\n\
 SIGNAL i_dp_clk   : STD_LOGIC := '1';\n"
 
-s_connect_mm_clk = "mm_clk   <= i_mm_clk;\n"
-s_connect_dp_clk = "dp_clk   <= i_dp_clk;\n"
+s_inv_mm_rst = "mm_rst_n <= NOT(mm_rst);\n"
 
 s_fileio_start = "----------------------------------------------------------------------------\n\
 -- MM <-> file I/O for simulation. The files are created in $UPE/sim.\n\
@@ -205,10 +204,10 @@ class QsysEntity(vhdl.Entity):
 
             if "_reset_export" in s:  
                 s_connect =  "OPEN,"
-                
+
             # Exceptions for the ethernet
-            if "tse_clk" in s:  
-                s_connect =  "eth1g_tse_clk,"
+            if "eth1g_mm_clk_export" in s:  
+                s_connect =  "OPEN," #"eth1g_tse_clk,"
 
             if "eth1g_mm_rst_export" in s:  
                 s_connect =  "eth1g_mm_rst,"
@@ -232,7 +231,7 @@ class QsysEntity(vhdl.Entity):
                 s_connect =  "mm_clk,"
 
             if s == "reset_in_reset_n":  
-                s_connect =  "mm_rst,"
+                s_connect =  "mm_rst_n,"
 
             if "_phasedone_export" in s:  
                 s_connect =  "OPEN,"
@@ -281,7 +280,7 @@ class MmmEntity(vhdl.Entity):
             
             # Extra signals for ethernet peripheral
             if(s[0] == "eth1g_ram"): 
-                self.add_port("eth1g_tse_clk",       "OUT", "STD_LOGIC")      
+                #self.add_port("eth1g_tse_clk",       "OUT", "STD_LOGIC")      
                 self.add_port("eth1g_mm_rst",        "OUT", "STD_LOGIC")    
                 self.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC")   
             
@@ -412,6 +411,7 @@ if __name__ == '__main__':
                     ['sim_eth_psc_access',    'STD_LOGIC',  ''],
                     ['i_eth1g_reg_mosi',      't_mem_mosi', ''],
                     ['i_eth1g_reg_miso',      't_mem_miso', ''],
+                    ['mm_rst_n',              'STD_LOGIC',  ''],
                     ['sim_eth1g_reg_mosi',    't_mem_mosi', '']]
 
     for s in arch_constants:
@@ -436,8 +436,8 @@ if __name__ == '__main__':
     s_file    = s_fileio_start + ent_qsys.apply_indend(s_arch_file + s_fileio_eth_init + s_fileio_poll, 2) + s_end_generate + "\n"
 
     # Make QSYS master
-    s_master_start = s_master_header + "gen_" + ent_qsys.name + " : IF g_sim = FALSE GENERATE\n" 
-    s_master = s_master_start + ent_qsys.apply_indend(ent_qsys.make_qsys_instance_string(mmm_conf), 2) + s_end_generate + "\n"
+    s_master_start = s_master_header + "gen_" + ent_qsys.name + " : IF g_sim = FALSE GENERATE\n" + "\n"
+    s_master = s_master_start + ent_qsys.apply_indend(s_inv_mm_rst + "\n" + ent_qsys.make_qsys_instance_string(mmm_conf), 2) + s_end_generate + "\n"
 
     s_arch_total = s_arch_begin + ent_qsys.apply_indend(s_file + s_master, 2) + s_arch_end
     string_elements = [s_header, s_instantiation, s_libraries, s_entity, s_arch_header, s_arch_total ]