Added entry for pps.

Connected cal_clk form mmm agin. Disbaled cal_clk from ctrl_unb1_board.
CHanged nof_blocks form 781250 to 800000

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd

@@ -117,7 +117,7 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
   CONSTANT c_use_bg                 : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_tp_bg"; -- Also use DDR3, but no mesh terminals
   CONSTANt c_use_bf                 : BOOLEAN := NOT(g_design_name="apertif_unb1_fn_beamformer_tp_bg" AND g_sim);
   CONSTANT c_use_phy                : t_c_unb1_board_use_phy  := (1, 1, sel_a_b(c_use_bg, 0, 1), 0, sel_a_b(c_use_transpose, 1, 0), 0, 0, 1); 
-  CONSTANT c_fw_version             : t_unb1_board_fw_version := (3, 5);  -- firmware version x.y
+  CONSTANT c_fw_version             : t_unb1_board_fw_version := (3, 8);  -- firmware version x.y
   CONSTANT c_tr_mesh                : t_c_unb1_board_tr       := c_unb1_board_tr_mesh;
   CONSTANT c_dp_clk_use_pll         : BOOLEAN := g_design_name="apertif_unb1_fn_beamformer_base";
 
@@ -144,7 +144,7 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
   -- PIOs
   SIGNAL pout_debug_wave            : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL pout_wdi                   : STD_LOGIC;
-  SIGNAL pin_pps                    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
   SIGNAL pin_intab                  : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
   SIGNAL pout_intab                 : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
 
@@ -188,7 +188,7 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
   CONSTANT c_rd_nof_chunks      : NATURAL := 11;  --15 for 6-bit or 11 for 8-bit 
   CONSTANT c_rd_interval        : NATURAL := c_rd_chunksize;
   CONSTANT c_gapsize            : NATURAL := 0; 
-  CONSTANT c_nof_blocks         : NATURAL := sel_a_b(g_sim, 16, 781250); --800000);
+  CONSTANT c_nof_blocks         : NATURAL := sel_a_b(g_sim, 16, 800000); --800000  781250);
   
   CONSTANT c_reorder_seq_conf   : t_reorder_seq := (c_wr_chunksize, 
                                                     c_rd_chunksize, 
@@ -227,6 +227,9 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
   -- . UniBoard I2C sens
   SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
   SIGNAL reg_unb_sens_miso          : t_mem_miso;   
+  -- PPSH                                        
+  SIGNAL reg_ppsh_mosi              : t_mem_mosi;  
+  SIGNAL reg_ppsh_miso              : t_mem_miso;  
   -- . eth1g
   SIGNAL eth1g_tse_clk              : STD_LOGIC;
   SIGNAL eth1g_mm_rst               : STD_LOGIC;
@@ -320,7 +323,7 @@ BEGIN
     g_udp_offload             => TRUE, 
     g_aux                     => c_unb1_board_aux,
     g_udp_offload_nof_streams => c_eth_nof_udp_ports,  
-    g_xo_clk_use_pll          => TRUE 
+    g_xo_clk_use_pll          => FALSE 
   )
   PORT MAP (
     -- Clock an reset signals
@@ -332,7 +335,6 @@ BEGIN
     mm_clk                   => mm_clk,
     mm_locked                => mm_locked,
     mm_rst                   => mm_rst,
-    cal_rec_clk              => cal_rec_clk,
 
     dp_rst                   => ctrl_dp_rst,
     dp_clk                   => ctrl_dp_clk,
@@ -361,6 +363,10 @@ BEGIN
     reg_unb_sens_mosi        => reg_unb_sens_mosi,
     reg_unb_sens_miso        => reg_unb_sens_miso,    
     
+    -- . PPSH
+    reg_ppsh_mosi            => reg_ppsh_mosi,
+    reg_ppsh_miso            => reg_ppsh_miso,
+    
     -- eth1g
     eth1g_tse_clk            => eth1g_tse_clk,   -- 125 MHz from xo_clk PLL in SOPC system
     eth1g_mm_rst             => eth1g_mm_rst,
@@ -785,10 +791,9 @@ BEGIN
     mm_rst         => mm_rst,                      
     mm_clk         => mm_clk,                      
     mm_locked      => mm_locked,                   
-    cal_clk        => cal_clk,                     
+    cal_clk        => cal_rec_clk,                     
 
     pout_wdi       => pout_wdi,                    
-    pin_pps        => pin_pps,                     
     
     -- Manual WDI override
     reg_wdi_mosi               => reg_wdi_mosi,                  
@@ -804,6 +809,10 @@ BEGIN
     reg_unb_sens_mosi          => reg_unb_sens_mosi,              
     reg_unb_sens_miso          => reg_unb_sens_miso,   
     
+    -- PPSH
+    reg_ppsh_mosi              => reg_ppsh_mosi,
+    reg_ppsh_miso              => reg_ppsh_miso, 
+
     -- Diagnostics             
     reg_diagnostics_mosi       => reg_diagnostics_mosi,           
     reg_diagnostics_miso       => reg_diagnostics_miso,