added reg_fpga_sens_* mm

boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd

@@ -76,6 +76,9 @@ ENTITY mmm_unb2_test IS
     reg_unb_sens_mosi        : OUT t_mem_mosi; 
     reg_unb_sens_miso        : IN  t_mem_miso; 
                              
+    reg_fpga_sens_mosi       : OUT t_mem_mosi;
+    reg_fpga_sens_miso       : IN  t_mem_miso;
+
     -- PPSH
     reg_ppsh_mosi            : OUT t_mem_mosi; 
     reg_ppsh_miso            : IN  t_mem_miso; 
@@ -265,9 +268,12 @@ ARCHITECTURE str OF mmm_unb2_test IS
   SIGNAL sim_eth_mm_bus_switch                     : STD_LOGIC;
   SIGNAL sim_eth_psc_access                        : STD_LOGIC;
 
+  SIGNAL i_eth1g_eth0_reg_mosi                     : t_mem_mosi;
+  SIGNAL i_eth1g_eth0_reg_miso                     : t_mem_miso;
   SIGNAL i_eth1g_eth1_reg_mosi                     : t_mem_mosi;
   SIGNAL i_eth1g_eth1_reg_miso                     : t_mem_miso;
 
+  SIGNAL sim_eth1g_eth0_reg_mosi                   : t_mem_mosi;
   SIGNAL sim_eth1g_eth1_reg_mosi                   : t_mem_mosi;
   SIGNAL i_reset_n                                 : STD_LOGIC;
 
@@ -310,6 +316,9 @@ BEGIN
     u_mm_file_reg_unb_sens          : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
                                                  PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
 
+    u_mm_file_reg_fpga_sens         : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_SENS")
+                                                 PORT MAP(mm_rst, mm_clk, reg_fpga_sens_mosi, reg_fpga_sens_miso );
+
     u_mm_file_reg_ppsh              : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
                                                  PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
 
@@ -379,9 +388,9 @@ BEGIN
                                                            
     -- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
     u_mm_file_reg_eth0            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
+                                               PORT MAP(mm_rst, mm_clk, i_eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
     u_mm_file_reg_eth1            : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_1_MMS_REG")
-                                               PORT MAP(mm_rst, mm_clk, eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
+                                               PORT MAP(mm_rst, mm_clk, i_eth1g_eth1_reg_mosi, eth1g_eth1_reg_miso);
 
     u_mm_file_reg_tr_10GbE_qsfp_ring : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE_QSFP_RING")
                                                   PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_qsfp_ring_mosi, reg_tr_10GbE_qsfp_ring_miso);
@@ -404,25 +413,25 @@ BEGIN
     BEGIN
       sim_eth_mm_bus_switch <= '1';
 
-      eth1g_eth1_tse_mosi.wr <= '0';
-      eth1g_eth1_tse_mosi.rd <= '0';
+      eth1g_eth0_tse_mosi.wr <= '0';
+      eth1g_eth0_tse_mosi.rd <= '0';
       WAIT FOR 400 ns;
       WAIT UNTIL rising_edge(mm_clk);
-      proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth1_tse_miso, eth1g_eth1_tse_mosi);
+      proc_tech_tse_setup(c_tech_arria10, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_eth0_tse_miso, eth1g_eth0_tse_mosi);
 
       -- Enable RX
-      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth1_reg_miso, sim_eth1g_eth1_reg_mosi);  -- control rx en
+      proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_eth0_reg_miso, sim_eth1g_eth0_reg_mosi);  -- control rx en
       sim_eth_mm_bus_switch <= '0';
 
       WAIT;
     END PROCESS;
 
-    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth1_reg_mosi, i_eth1g_eth1_reg_mosi)
+    p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_eth0_reg_mosi, i_eth1g_eth0_reg_mosi)
     BEGIN
       IF sim_eth_mm_bus_switch = '1' THEN
-          eth1g_eth1_reg_mosi <= sim_eth1g_eth1_reg_mosi;
+          eth1g_eth0_reg_mosi <= sim_eth1g_eth0_reg_mosi;
         ELSE
-          eth1g_eth1_reg_mosi <= i_eth1g_eth1_reg_mosi;
+          eth1g_eth0_reg_mosi <= i_eth1g_eth0_reg_mosi;
         END IF;
     END PROCESS;
 
@@ -498,6 +507,14 @@ BEGIN
       reg_unb_sens_read_export                  => reg_unb_sens_mosi.rd,
       reg_unb_sens_readdata_export              => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
 
+      reg_fpga_sens_reset_export                => OPEN,
+      reg_fpga_sens_clk_export                  => OPEN,
+      reg_fpga_sens_address_export              => reg_fpga_sens_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_fpga_sens_adr_w-1 DOWNTO 0),
+      reg_fpga_sens_write_export                => reg_fpga_sens_mosi.wr,
+      reg_fpga_sens_writedata_export            => reg_fpga_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_fpga_sens_read_export                 => reg_fpga_sens_mosi.rd,
+      reg_fpga_sens_readdata_export             => reg_fpga_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+
       rom_system_info_reset_export              => OPEN,
       rom_system_info_clk_export                => OPEN,
       rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 

boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd

@@ -189,11 +189,12 @@ ARCHITECTURE str OF unb2_test IS
 
   -- Block generator constants
   CONSTANT c_bg_block_size              : NATURAL := 900;
-  CONSTANT c_bg_gapsize                 : NATURAL := 100;
+  CONSTANT c_bg_gapsize_1GbE            : NATURAL := 1000;
+  CONSTANT c_bg_gapsize_10GbE           : NATURAL := 100;
   CONSTANT c_bg_blocks_per_sync         : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
 
   CONSTANT c_use_jumbo_frames           : BOOLEAN := FALSE;
-  CONSTANT c_def_1GbE_block_size        : NATURAL := 0;   -- 0 first so we have time to set RX demux reg in dest. node
+  CONSTANT c_def_1GbE_block_size        : NATURAL := 20;   -- 0 first so we have time to set RX demux reg in dest. node
   CONSTANT c_def_10GbE_block_size       : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
 
   CONSTANT c_max_frame_len              : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
@@ -252,6 +253,10 @@ ARCHITECTURE str OF unb2_test IS
   SIGNAL reg_unb_sens_mosi          : t_mem_mosi;
   SIGNAL reg_unb_sens_miso          : t_mem_miso;
 
+  -- fpga sensors
+  SIGNAL reg_fpga_sens_mosi         : t_mem_mosi;
+  SIGNAL reg_fpga_sens_miso         : t_mem_miso;
+
   -- eth1g ch0
   SIGNAL eth1g_eth0_mm_rst          : STD_LOGIC;
   SIGNAL eth1g_eth0_tse_mosi        : t_mem_mosi;  -- ETH TSE MAC registers
@@ -504,6 +509,9 @@ BEGIN
     reg_unb_sens_mosi        => reg_unb_sens_mosi,
     reg_unb_sens_miso        => reg_unb_sens_miso,    
     
+    reg_fpga_sens_mosi       => reg_fpga_sens_mosi,
+    reg_fpga_sens_miso       => reg_fpga_sens_miso,
+
     -- . PPSH
     reg_ppsh_mosi            => reg_ppsh_mosi,
     reg_ppsh_miso            => reg_ppsh_miso,
@@ -585,6 +593,9 @@ BEGIN
     reg_unb_sens_mosi        => reg_unb_sens_mosi,
     reg_unb_sens_miso        => reg_unb_sens_miso, 
  
+    reg_fpga_sens_mosi       => reg_fpga_sens_mosi,
+    reg_fpga_sens_miso       => reg_fpga_sens_miso,    
+
     -- PPSH
     reg_ppsh_mosi            => reg_ppsh_mosi,
     reg_ppsh_miso            => reg_ppsh_miso, 
@@ -727,8 +738,8 @@ BEGIN
       g_sim                       => g_sim,
       g_nof_streams               => c_nof_streams_1GbE,
       g_data_w                    => c_data_w_32,
-      g_bg_block_size             => c_bg_block_size,
-      g_bg_gapsize                => c_bg_gapsize,
+      g_bg_block_size             => c_def_1GbE_block_size,
+      g_bg_gapsize                => c_bg_gapsize_1GbE,
       g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
       g_def_block_size            => c_def_1GbE_block_size,
       g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
@@ -800,8 +811,8 @@ BEGIN
       g_sim                       => g_sim,
       g_nof_streams               => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
       g_data_w                    => c_data_w_64,
-      g_bg_block_size             => c_bg_block_size,
-      g_bg_gapsize                => c_bg_gapsize,
+      g_bg_block_size             => c_def_10GbE_block_size,
+      g_bg_gapsize                => c_bg_gapsize_10GbE,
       g_bg_blocks_per_sync        => c_bg_blocks_per_sync,
       g_def_block_size            => c_def_10GbE_block_size,
       g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_10GbE,