-Added corr_output_framer to correlator output.

libraries/dsp/correlator/hdllib.cfg

@@ -16,6 +16,7 @@ synth_files =
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
+    $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
     $SVN/RadioHDL/trunk/libraries/dsp/correlator/src/vhdl/correlator.vhd
 
 test_bench_files = 

libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Purpose:
+-- . Add SOP, EOP, BSN, SYNC and CHANNEL fields to correlator output.
+-- Description:
+-- . dp_block_gen generates the SOP, EOP, BSN and SYNC
+-- . A clocked process adds the correct channel.
+
+ENTITY corr_output_framer IS
+  GENERIC (
+    g_nof_inputs          : NATURAL := 1;  -- Number of inputs
+    g_nof_words_per_frame : NATURAL;       -- Nof words per frame
+    g_nof_frames_per_sync : NATURAL;
+    g_nof_channels        : NATURAL
+  );
+  PORT (
+    rst            : IN  STD_LOGIC;
+    clk            : IN  STD_LOGIC;
+
+    snk_in_arr     : IN  t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+    src_out_arr    : OUT t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0)
+  );
+END corr_output_framer;
+
+ARCHITECTURE str OF corr_output_framer IS
+
+  SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+  SIGNAL channel_src_out_arr      : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+  SIGNAL nxt_channel_src_out_arr  : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- Add SOP and EOP to mux output
+  -----------------------------------------------------------------------------
+  gen_dp_block_gen : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+    u_dp_block_gen: ENTITY dp_lib.dp_block_gen
+    GENERIC MAP (
+      g_use_src_in         => FALSE,
+      g_nof_data           => g_nof_words_per_frame,
+      g_nof_blk_per_sync   => g_nof_frames_per_sync 
+    )
+    PORT MAP (
+      rst        => rst,
+      clk        => clk,
+  
+      snk_in     => snk_in_arr(i),
+  
+      src_out    => dp_block_gen_src_out_arr(i)
+    );
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- Assign the channel field
+  -----------------------------------------------------------------------------
+  p_channel : PROCESS(dp_block_gen_src_out_arr)
+  BEGIN
+    FOR i IN 0 TO g_nof_inputs-1 LOOP
+      nxt_channel_src_out_arr(i).channel <= channel_src_out_arr(i).channel;
+      IF dp_block_gen_src_out_arr(i).eop='1' THEN
+        IF channel_src_out_arr(i).channel = TO_DP_CHANNEL(g_nof_channels-1) THEN
+          nxt_channel_src_out_arr(i).channel <= TO_DP_CHANNEL(0);
+        ELSE
+          nxt_channel_src_out_arr(i).channel <= INCR_UVEC(channel_src_out_arr(i).channel, 1);
+        END IF;
+      END IF;
+    END LOOP;
+  END PROCESS;
+
+  -- Registers
+  p_clk: PROCESS(clk, rst)
+  BEGIN
+    IF rst='1' THEN
+      channel_src_out_arr <= (OTHERS=>c_dp_sosi_rst);
+    ELSIF rising_edge(clk) THEN
+      channel_src_out_arr <= nxt_channel_src_out_arr;
+    END IF;
+  END PROCESS;
+
+  -----------------------------------------------------------------------------
+  -- Add channel field to dp_block_gen_src_out_arr and forward to snk_out_arr
+  -----------------------------------------------------------------------------
+  p_wires : PROCESS(dp_block_gen_src_out_arr, channel_src_out_arr)
+  BEGIN
+    src_out_arr <= dp_block_gen_src_out_arr;
+    FOR i IN 0 TO g_nof_inputs-1 LOOP
+      src_out_arr(i).channel <= channel_src_out_arr(i).channel;
+    END LOOP;
+  END PROCESS;
+
+END str;
+

libraries/dsp/correlator/src/vhdl/correlator.vhd

@@ -307,21 +307,22 @@ BEGIN
   );
 
   -----------------------------------------------------------------------------
-  -- Add proper SOP and EOP to mux output
+  -- Add SOP, EOP, BSN, Channel and sync to tag the correlator output
   -----------------------------------------------------------------------------
-  dp_block_gen: ENTITY dp_lib.dp_block_gen
+  u_corr_output_framer : ENTITY work.corr_output_framer
   GENERIC MAP (
-    g_use_src_in         => FALSE,
-    g_nof_data           => c_nof_mults*pow2(g_nof_pre_mult_folds),
-    g_nof_blk_per_sync   => c_nof_visibilities*g_nof_channels -- Tags the integration period 
+    g_nof_inputs          => 1,
+    g_nof_words_per_frame => c_nof_visibilities, --c_nof_mults*pow2(g_nof_pre_mult_folds),
+    g_nof_channels        => g_nof_channels,
+    g_nof_frames_per_sync => g_nof_channels
   )
   PORT MAP (
-    rst        => rst,
-    clk        => clk,
+    rst         => rst,
+    clk         => clk,
 
-    snk_in     => corr_folder_src_out_arr(0),
+    snk_in_arr  => corr_folder_src_out_arr,
 
-    src_out    => src_out_arr(0)
+    src_out_arr => src_out_arr
   );
 
 END str;