Ready for review.

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd

@@ -72,7 +72,7 @@ ARCHITECTURE rtl OF ddrctrl_input_repack IS
   c_v_count                 : NATURAL;                                                                                                        -- the amount of times the c_v vector received data from the input since the last time it was filled completely
   s_out_bsn_ds              : NATURAL;
   s_out_bsn                 : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-  output_passed             : STD_LOGIC;
+  output_passed             : STD_LOGIC;                                                                                                      -- this signal is to make sure that out_bsn_written only gets low after a write cycle, this is so that ddrctrl_address_counter can save the address at which the data corresponding to the bsn is saved
   out_data_count            : NATURAL;                                                                                                        -- the amount of times the output data vector has been filled since the last time c_v was filled completely
   out_bsn_written           : STD_LOGIC;                                                                                                      -- this signal gets high ones the out_bsn signal is updated, this is so in ddrctrl_input_address_counter the right address can be linked with the out_bsn signal
   out_of                    : NATURAL;                                                                                                        -- this is the amount of bits that the first data word(168) is shifted from the first bit in the data word(576)