Add ideas, answers, decisions.

applications/lofar2/doc/prestudy/lift_sdp_transient_buffer.txt

@@ -40,3 +40,6 @@ b) Transient detection:
 
 
 - Waarom kan LIFT niet commensal met BF?
+
+  --> during thunderstorm BF measurements get disturbed anyway
+  --> For maximum transport capacity to CEP

applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt

@@ -60,3 +60,112 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
 - Buffer lengte versus nof antennes
 - Self trigger
 
+3) Design
+
+- buffer raw data, no need to buffer subbands
+- no self triggering yet for MVP
+
+- Station --> CEP --> Data Writer
+  . SDP output UDP directly to CEP or to LCU so that LCU can pass it on via TCP, to
+    recover from data loss
+  . SDP output via 10GbE
+  . SDP CP for speed dial output, to avoid data loss
+
+- treat all signal inputs independently (even though X and Y are always needed together)
+
+- CP per signal input buffer
+  . flexible start and end address (so flexible buffer time per signal input)
+  . freeze, unfreeze
+  . no need to whipe (zero) buffer contents after unfreeze ?
+
+- support MP on buffer state
+  . signal input index
+  . frozen, buffering, reading
+  . start address (time), end address (time)
+
+- Provide direct MM access interface to DDR4
+  . New access multiplexer component to interface with io_ddr with:
+    . write 12 signal input streams + 1 MM write stream
+    . read 1 stream for TB readout + 1 MM read stream
+  . Write multiplexer for 12 + 1 = 13 inputs will take ~100 M20K,
+    because it needs to multiplex and FIFO streams of 256 bit each and
+    256 bit requires 256 /40 = 7 M20K in parallel, so 13 * 7 = 91 M20K.
+
+Use 1 DDR4 module / FPGA
+  . Because 16GB is enough for T_tbuf = 3.3 s
+  . 1 DDR4 @ 200MHz yields 200MHz * 256b/8b = 6.4 GB/s maximum write
+    access. Samples data from 12 ADCs is 12 * 200MHz * 16b/8b = 4.8 GB/s.
+    Hence the TB function then uses 4.8 / 6.4 = 0.75 of the capacity,
+    which is fine and leaves sufficient spare capacity for some buffer
+    read out, because 10Gbps / 8b = maximum 1.2 GB/s.
+  . If we would use 2 DDR4 modules/ FPGA, then treat them as one big
+    buffer with extended address space by DDR4 II, so use them
+    sequentially, rather than in parallel, and to still have full
+    freedom of allocationg memory space to signal inputs.
+
+- support partial dump
+  . lightning >~ 1 s, cosmic ray >~ 1 ms
+  . dump t0 - t1
+  . dump last dt
+
+- packetize voor buffer write of na buffer read? --> voor
+  . packtetize at 64b or 256b ?
+  . 16b -> 64b packetize --> 64b --> 256b store
+  . data in buffer must have CRC --> 64b CRC ?
+
+- dp_offload_tx header is the same for all 12 signal inputs, only si differs,
+  so create one header for all and modify si field to save logic and RAM
+- 12 input multiplexer with 12 x 256b in and 256b out to write 256b words @ 200 MHz
+- use SSN as timestamp, SSN = BSN * N_fft, so can be derived from bsn_source BSN,
+  or do we need a dp_ssn_source.vhd?
+
+- unb2c_test_ddr_16G resource usage
+  . git/hdl/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G_resource_usage.jpg
+  . per module:
+    wr_fifo 13 M20K
+    tech_ddr 9 M20K
+    rd_fifo  4 M20K
+    diag db  0 M20K
+    diag bg  0 M20K
+    --> Total 26 M20K/DDR4 module
+  . board common:
+    MMM : 69 M20K voor Nios memory
+    ctrl: 42 M20K voor MMAP ROM en 1GbE
+
+- store and send 14b packed data
+  . so do not use 16b (with 2b sign extension), to optimize for memory usage and
+    transport capacity (at the expense of requiring tools to observe the payload
+    contents).
+  . store application packet with CRC in DDR4
+  . store packed 14b data for 16/14 = 1.14 more buffer space (3.3s --> 3.8s)
+  . send unpacked 16b data to CEP with new CRC
+  . CRC = 64b, header multiple of 64b, nof samples per payload multiple of 64b
+
+- Maximum number of packets per dump
+  . max memory size 16GB
+  . max payload size 8kB
+  --> 16G / 8k = 2M packets --> log2(2e6) = 20.93b
+  . use packet serial number, instead of sop, eop bit fields, to show progress of
+    the packet dump to CEP
+
+- application header fields:
+  . 8b marker
+  . 8b version_id
+  . 16b station_id
+  . 32b source_info
+    - 1b antenna_band_index
+    - 1b nyquist_zone_index
+    - 1b f_adc --> sample period is 5 ns or 6.25 ns
+    - 1b payload_error --> based on DDR4 read CRC
+    - 5b sample_width --> 14b
+  . 8b signal_input_index
+  . 16b nof_samples_per_packet
+  . 24b packet serial number in current dump
+  . 24b total nof packets in current dump
+  . 64b SSN = Sample Sequence Number
+  No need for:
+    - 32b observation_id --> also not in LOFAR1
+    - 5b gn_index --> signal_input_index provides already all this information
+
+
+