Skip to content
Snippets Groups Projects
Commit 1807e4aa authored by Jan Oudman's avatar Jan Oudman
Browse files

renamed some signals. Prepared a generic for a debug mode in st_histogram_8_april

parent e89cd857
No related branches found
No related tags found
2 merge requests!43Master,!21Resolve L2SDP-88
Show whitespace changes
Inline Side-by-side
libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd
+ 37
− 33
View file @ 1807e4aa
......@@ -13,6 +13,7 @@ ENTITY st_histogram_8_april IS
g_in_data_w : NATURAL := 14; -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768) <-- maybe just g_data_w ??
g_nof_bins : NATURAL := 512; -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
g_nof_data : NATURAL
-- g_ram_miso_dbg_mode : BOOLEAN := FALSE -- when TRUE the ram_miso bus will get a copy of the data written into the RAM.
);
PORT (
dp_rst : IN STD_LOGIC;
......@@ -58,6 +59,7 @@ ARCHITECTURE rtl OF st_histogram_8_april IS
SIGNAL bin_arbiter_rd_mosi : t_mem_mosi;
SIGNAL bin_arbiter_rd_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL bin_reader_rd_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL common_ram_r_w_0_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL init_phase : STD_LOGIC := '1';
......@@ -76,8 +78,8 @@ ARCHITECTURE rtl OF st_histogram_8_april IS
SIGNAL same_r_w_address_pp : STD_LOGIC;
--pipelined signals
SIGNAL dp_pipeline_src_out_p : t_dp_sosi;
SIGNAL dp_pipeline_src_out_pp : t_dp_sosi;
SIGNAL snk_in_p : t_dp_sosi;
SIGNAL snk_in_pp : t_dp_sosi;
SIGNAL prev_bin_reader_mosi : t_mem_mosi := c_mem_mosi_rst ;
SIGNAL bin_reader_mosi_pp : t_mem_mosi := c_mem_mosi_rst;
SIGNAL bin_reader_mosi_ppp : t_mem_mosi := c_mem_mosi_rst;
......@@ -94,13 +96,14 @@ BEGIN
-----------------------------------------------------------------------------
-- Bin reader: Convert snk_in data to bin_reader_mosi with read request
-- . in : snk_in (latency: 0)
-- . in : bin_arbiter_rd_miso (latency: 2)
-- . out : init_phase (latency: 0 ?
-- . out : bin_reader_mosi (latency: 0)
-- . out : prev_bin_reader_mosi (latency: 1)
-- . out : bin_reader_mosi_pp (latency: 2)
-- . out : bin_reader_mosi_ppp (latency: 3)
-- . out : bin_reader_rd_miso (latency: 2)
-- - out : rd_cnt_allowed_pp (latency: 2)
-- . out : dp_pipeline_src_out_pp (latency: 2) -- unnecesary
-- . out : same_r_w_address_pp (latency: 2)
-- . out : toggle_detect_pp (latency: 2)
-- . out : sync_detect (latency: 0)
......@@ -108,6 +111,7 @@ BEGIN
-----------------------------------------------------------------------------
bin_reader_mosi.rd <= snk_in.valid; -- when 1, count allowed
bin_reader_mosi.address(c_adr_w-1 DOWNTO 0) <= snk_in.data(g_in_data_w-1 DOWNTO c_adr_low);
bin_reader_rd_miso <= bin_arbiter_rd_miso;
--snk_in pipeline; Enable sync and valid comparisons
u_dp_pipeline_snk_in_1_cycle : ENTITY dp_lib.dp_pipeline
......@@ -118,10 +122,10 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_in => snk_in,
src_out => dp_pipeline_src_out_p
src_out => snk_in_p
);
init_phase <= '0' WHEN dp_pipeline_src_out_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
init_phase <= '0' WHEN snk_in_p.sync = '1'; -- ELSE will be impossible since the init_phase may only be triggered once on the first sync
-- Enable sync comparisons
u_dp_pipeline_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline
......@@ -132,13 +136,13 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_in => snk_in,
src_out => dp_pipeline_src_out_pp
src_out => snk_in_pp
);
dbg_snk_data <= dp_pipeline_src_out_pp.data(g_in_data_w-1 DOWNTO 0);
dbg_snk_data <= snk_in_pp.data(g_in_data_w-1 DOWNTO 0);
toggle_detect_false <= '0' WHEN dp_pipeline_src_out_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1' OR dp_pipeline_src_out_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
toggle_detect_false <= '0' WHEN snk_in_pp.sync = '1'; -- ELSE will be impossible since the toggle_detect_false may only be triggered once on the first sync
sync_detect <= snk_in.valid WHEN (snk_in.sync='1' OR snk_in_p.sync='1' OR snk_in_pp.sync='1') ELSE '0'; -- @sync, first 3 cycles would try to read from the wrong (old) RAM block, detect this problem
-- Line up to p_nxt_bin_writer_mosi process
u_common_pipeline_sl_sync_detect_2_cycle : ENTITY common_lib.common_pipeline_sl
......@@ -197,7 +201,7 @@ BEGIN
-- Only count sequential valid data on the same address when: address is the same as last and 1 or 2 cycles after the sync when in sync_detect; address is the same as last and past the initialisation and outside sync_detect
rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( (dp_pipeline_src_out_p.sync='1' AND dp_pipeline_src_out_p.valid='1') OR (dp_pipeline_src_out_pp.sync='1' AND dp_pipeline_src_out_p.valid='1') ) )
rd_cnt_allowed <= snk_in.valid WHEN ( bin_reader_mosi.address = prev_bin_reader_mosi.address AND ( (snk_in_p.sync='1' AND snk_in_p.valid='1') OR (snk_in_pp.sync='1' AND snk_in_p.valid='1') ) )
OR (bin_reader_mosi.address = prev_bin_reader_mosi.address AND init_phase='0' AND sync_detect='0')
ELSE '0';
......@@ -213,7 +217,7 @@ BEGIN
);
-- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync --also @sync, one wil be true; use NOT(1 or 1) instead of (0 or 0)
toggle_detect <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1') )
toggle_detect <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR snk_in_p.sync='1') )
ELSE '0';
......@@ -245,25 +249,24 @@ BEGIN
-----------------------------------------------------------------------------
-- Bin writer : increments current bin value and sets up write request
-- . in : dp_pipeline_src_out_pp (latency: 2) -- unnecesary ?
-- . in : toggle_detect_pp (latency: 2)
-- . in : same_r_w_address_pp (latency: 2)
-- . in : bin_reader_mosi_pp (latency: 2)
-- . in : bin_arbiter_rd_miso (latency: 2) common_ram_r_w_0_miso
-- . in : bin_reader_rd_miso (latency: 2) aka bin_arbiter_rd_miso or common_ram_r_w_0_miso
-- . in : rd_cnt_allowed_pp (latency: 2)
-- . in : sync_detect_pp
-- . out : bin_writer_mosi (latency: 3)
-----------------------------------------------------------------------------
p_nxt_bin_writer_mosi : PROCESS(bin_arbiter_rd_miso,
bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS -- dp_pipeline_src_out_pp necesary?? init_phase unnecesary? ; removed: common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
p_nxt_bin_writer_mosi : PROCESS(bin_reader_rd_miso,
bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp) IS -- init_phase unnecesary? ; removed: common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata,
BEGIN
nxt_bin_writer_mosi <= c_mem_mosi_rst;
dbg_state_string <= "unv";
IF bin_arbiter_rd_miso.rdval='1' THEN -- common_ram_r_w_0_miso
IF bin_reader_rd_miso.rdval='1' THEN -- common_ram_r_w_0_miso
nxt_bin_writer_mosi.wr <= '1';
nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_arbiter_rd_miso.rddata, 1); -- common_ram_r_w_0_miso
nxt_bin_writer_mosi.wrdata <= INCR_UVEC(bin_reader_rd_miso.rddata, 1); -- common_ram_r_w_0_miso
nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
nxt_prev_wrdata <= TO_UINT(bin_arbiter_rd_miso.rddata) + 1; -- common_ram_r_w_0_miso
nxt_prev_wrdata <= TO_UINT(bin_reader_rd_miso.rddata) + 1; -- common_ram_r_w_0_miso
dbg_state_string <= "val";
ELSIF toggle_detect_pp = '1' THEN
......@@ -282,7 +285,7 @@ BEGIN
ELSIF sync_detect_pp = '1' THEN
nxt_bin_writer_mosi.wr <= '1';
nxt_bin_writer_mosi.wrdata <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; dp_pipeline_src_out_p.sync (thus new adress): 1; dp_pipeline_src_out_pp.sync (thus new adress): 1
nxt_bin_writer_mosi.wrdata <= TO_UVEC(1, c_mem_data_w); -- snk_in.sync: 1; snk_in_p.sync (thus new adress): 1; snk_in_pp.sync (thus new adress): 1
nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
nxt_prev_wrdata <= 1;
dbg_state_string <= "sd ";
......@@ -296,7 +299,7 @@ BEGIN
END IF;
END PROCESS;
p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS
p_bin_writer_mosi : PROCESS(dp_clk, dp_rst, nxt_bin_writer_mosi, nxt_prev_wrdata, prev_wrdata, prev_prev_wrdata) IS --really only dp_clk &rst necessary?
BEGIN
IF dp_rst = '1' THEN
bin_writer_mosi <= c_mem_mosi_rst;
......@@ -323,6 +326,7 @@ BEGIN
-- : bin_reader_mosi_ppp (latency: 3)
-- : bin_writer_mosi (latency: 3)
-- : sync_detect (latency: 0? or 3?
-- : common_ram_r_w_0_miso (latency: 2)
-- . out : bin_arbiter_rd_mosi (latency: 1)
-- . : bin_arbiter_rd_miso (latency: 2)
-- . : bin_arbiter_wr_mosi (latency: 4)
......
libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+ 19
− 33
View file @ 1807e4aa
......@@ -144,23 +144,19 @@ ARCHITECTURE tb OF tb_st_histogram IS
----------------------------------------------------------------------------
-- Self check array
----------------------------------------------------------------------------
TYPE t_data_check_arr IS ARRAY (0 TO g_nof_bins) OF INTEGER; -- 0 TO g_nof_bins -- NATURAL RANGE <>
SIGNAL data_check_arr : t_data_check_arr := (OTHERS=> 0);-- (OTHERS=> 0)); -- := (1,1,1,1,0,1,1,1,1, 1, 1, 1, 1, 0, 1, 1, 1);
-- 1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16.17
TYPE t_data_check_arr IS ARRAY (0 TO g_nof_bins) OF INTEGER;
SIGNAL data_check_arr : t_data_check_arr := (OTHERS=> 0);
SIGNAL check_adr : NATURAL := 0; --(g_data_w DOWNTO c_adr_low) : STD_LOGIC_VECTOR;
SIGNAL check_adr : NATURAL := 0;
SIGNAL prev_check_adr : NATURAL;
SIGNAL nxt_check_arr_cnt : NATURAL;
-- SIGNAL data_check_index_cnt : NATURAL := 0;
SIGNAL dp_pipeline_src_out_pp : t_dp_sosi;
SIGNAL dp_pipeline_src_out_ppp : t_dp_sosi;
SIGNAL dp_pipeline_src_out_pppp: t_dp_sosi;
SIGNAL st_histogram_snk_in_ppp : t_dp_sosi;
SIGNAL st_histogram_snk_in_pppp: t_dp_sosi;
-- SIGNAL dbg_check_adr :STD_LOGIC_VECTOR(g_data_w-1 DOWNTO c_adr_low); -- : NATURAL;
SIGNAL dbg_error_location : STD_LOGIC;
SIGNAL error_cnt : NATURAL; -- or variable
SIGNAL error_cnt : NATURAL;
SIGNAL dbg_int_data_miso : NATURAL;
SIGNAL dbg_int_data_arr : NATURAL;
......@@ -378,7 +374,7 @@ BEGIN
g_in_data_w => g_data_w,
g_nof_bins => g_nof_bins,
g_nof_data => g_nof_data
--g_str => g_str
--g_ram_miso_dbg_mode => TRUE
)
PORT MAP (
dp_rst => dp_rst,
......@@ -407,16 +403,6 @@ BEGIN
-- easily spotted in the wave window and a report is made.
----------------------------------------------------------------------------
u_dp_pipeline_st_histogram_snk_in_2_cycle : ENTITY dp_lib.dp_pipeline -- not used
GENERIC MAP (
g_pipeline => 2 -- 0 for wires, > 0 for registers,
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => st_histogram_snk_in,
src_out => dp_pipeline_src_out_pp
);
u_dp_pipeline_st_histogram_snk_in_3_cycle : ENTITY dp_lib.dp_pipeline
GENERIC MAP (
......@@ -426,7 +412,7 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_in => st_histogram_snk_in,
src_out => dp_pipeline_src_out_ppp
src_out => st_histogram_snk_in_ppp
);
u_dp_pipeline_st_histogram_snk_in_4_cycle : ENTITY dp_lib.dp_pipeline
......@@ -437,13 +423,13 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
snk_in => st_histogram_snk_in,
src_out => dp_pipeline_src_out_pppp
src_out => st_histogram_snk_in_pppp
);
---------------------------------------
-- create address from the source data
check_adr <= TO_UINT( dp_pipeline_src_out_ppp.data(g_data_w-1 DOWNTO c_adr_low) );
-- dbg_check_adr <= dp_pipeline_src_out_ppp.data(g_data_w -1 DOWNTO c_adr_low);
check_adr <= TO_UINT( st_histogram_snk_in_ppp.data(g_data_w-1 DOWNTO c_adr_low) );
-- dbg_check_adr <= st_histogram_snk_in_ppp.data(g_data_w -1 DOWNTO c_adr_low);
p_prev_check_adr : PROCESS (dp_rst, dp_clk, check_adr)
BEGIN
......@@ -456,12 +442,12 @@ BEGIN
-----------------------------
-- when valid increase array based on address
nxt_check_arr_cnt <= data_check_arr(check_adr) + 1 WHEN dp_pipeline_src_out_ppp.valid = '1' ELSE data_check_arr(check_adr);
nxt_check_arr_cnt <= data_check_arr(check_adr) + 1 WHEN st_histogram_snk_in_ppp.valid = '1' ELSE data_check_arr(check_adr);
--------------------
-- filling the array
p_cumulate_testdata : PROCESS (dp_rst, dp_clk, nxt_check_arr_cnt, check_adr, dp_pipeline_src_out_ppp.sync) --misses prev_check_adr
p_cumulate_testdata : PROCESS (dp_rst, dp_clk, nxt_check_arr_cnt, check_adr, st_histogram_snk_in_ppp.sync) --misses prev_check_adr
BEGIN
--PROCESS
--c_data_check_arr(check_adr) <= nxt_check_arr_cnt;
......@@ -470,7 +456,7 @@ BEGIN
ELSIF rising_edge(dp_clk) THEN
--data_check_arr(prev_check_adr) <= nxt_check_arr_cnt;
data_check_arr(check_adr) <= nxt_check_arr_cnt; --old timing
IF dp_pipeline_src_out_ppp.sync='1' THEN
IF st_histogram_snk_in_ppp.sync='1' THEN
data_check_arr(0 TO g_nof_bins) <= (check_adr => 1, OTHERS => 0 ); -- null except check_adr
--
END IF;
......@@ -495,7 +481,7 @@ BEGIN
-- --dbg_error_location <= '0';
-- --dbg_int_data_miso <= TO_UINT(st_histogram_ram_miso.rddata);
-- --dbg_int_data_arr <= data_check_arr(check_adr);
-- IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) AND dp_pipeline_src_out_pppp.valid='1' THEN
-- IF data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) AND st_histogram_snk_in_pppp.valid='1' THEN
-- dbg_error_location <= '1';
-- REPORT "The value written to the RAM is not what it should be. See signal 'dbg_int_data_arr'. The failure concerns the bin (and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
-- error_cnt <= error_cnt + 1;
......@@ -513,7 +499,7 @@ BEGIN
-- show the location of an error after a small delay (to prevent spikes) when the data written is not the same as the reference and only when the data was initially valid. Do not allow to be triggered at the testbench end.
dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) ) AND dp_pipeline_src_out_pppp.valid='1' AND tb_end='0' ) ELSE '0';
dbg_error_location <= '1' AFTER c_dp_clk_period/5 WHEN ( (data_check_arr(prev_check_adr) /= TO_UINT(st_histogram_ram_miso.rddata) ) AND st_histogram_snk_in_pppp.valid='1' AND tb_end='0' ) ELSE '0';
ASSERT dbg_error_location='0' REPORT "The value written to the RAM is not what it should be. Comparison failed on (bin and array) address: " &integer'image(prev_check_adr) SEVERITY ERROR;
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment