Support g_mm_w < 32bin sim.

libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd

@@ -37,6 +37,9 @@
 --   . Enable or re-enable count starts at a ref_sync.
 --   . MM read of a count shows the strobe count that is captured at a ref_sync
 --    (default input ref_sync = '1' when not used)
+-- * g_mm_w = c_word_w
+--   Default use g_mm_w = 32b for MM, but support < 32 to ease verification of
+--   count values > 2**g_mm_w.
 --
 -------------------------------------------------------------------------------
 -- REGMAP
@@ -68,6 +71,7 @@ USE common_lib.common_mem_pkg.ALL;
 
 ENTITY dp_strobe_total_count IS
   GENERIC (
+    g_mm_w           : NATURAL := c_word_w;
     g_nof_counts_max : NATURAL := 15;  -- fixed by REGMAP
     g_nof_counts     : NATURAL := 1;  -- actual nof counts, <= g_nof_counts_max
     g_count_w        : NATURAL := c_longword_w;  -- actual count width, max is c_longword_w due to two mm word width
@@ -96,7 +100,7 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
   -- Define the size of the MM slave register
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,
                                   adr_w    => ceil_log2(c_nof_words),
-                                  dat_w    => c_word_w,  -- Use MM bus data width = c_word_w = 32 for all MM registers
+                                  dat_w    => g_mm_w,  -- Use MM bus data width = c_word_w = 32 for all MM registers
                                   nof_dat  => c_nof_words,
                                   init_sl  => '0');
 
@@ -116,6 +120,7 @@ ARCHITECTURE rtl OF dp_strobe_total_count IS
 BEGIN
  
   ASSERT g_nof_counts <= g_nof_counts_max REPORT "Too many counters to fit REGMAP." SEVERITY FAILURE;
+  ASSERT g_count_w <= g_mm_w*2 REPORT "Too wide counter to fit REGMAP." SEVERITY FAILURE;
 
   mm_cnt_clr <= (reg_mosi.rd OR reg_mosi.wr) WHEN TO_UINT(reg_mosi.address(c_mm_reg.adr_w-1 DOWNTO 0)) = c_clear_adr ELSE '0' ;
 
@@ -173,13 +178,13 @@ BEGIN
 
   -- Register mapping
   gen_cnt : FOR I IN 0 TO g_nof_counts-1 GENERATE
-    gen_reg_32b : IF g_count_w <= c_word_w GENERATE
-      rd_reg((2*I + 1) * c_word_w - 1 DOWNTO (2*I + 0) * c_word_w) <= RESIZE_UVEC(hold_cnt_arr(I), c_word_w);  -- low part
-      rd_reg((2*I + 2) * c_word_w - 1 DOWNTO (2*I + 1) * c_word_w) <= (OTHERS=>'0');  -- high part (not used)
+    gen_reg_32b : IF g_count_w <= g_mm_w GENERATE
+      rd_reg((2*I + 1) * g_mm_w - 1 DOWNTO (2*I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w);  -- low part
+      rd_reg((2*I + 2) * g_mm_w - 1 DOWNTO (2*I + 1) * g_mm_w) <= (OTHERS=>'0');  -- high part (not used)
     END GENERATE;
-    gen_reg_64b : IF g_count_w > c_word_w GENERATE
-      rd_reg((2*I + 1) * c_word_w - 1 DOWNTO (2*I + 0) * c_word_w) <= hold_cnt_arr(I)(c_word_w-1 DOWNTO 0);  -- low part
-      rd_reg((2*I + 2) * c_word_w - 1 DOWNTO (2*I + 1) * c_word_w) <= RESIZE_UVEC(hold_cnt_arr(I)(g_count_w-1 DOWNTO c_word_w), c_word_w);  -- high part
+    gen_reg_64b : IF g_count_w > g_mm_w GENERATE
+      rd_reg((2*I + 1) * g_mm_w - 1 DOWNTO (2*I + 0) * g_mm_w) <= hold_cnt_arr(I)(g_mm_w-1 DOWNTO 0);  -- low part
+      rd_reg((2*I + 2) * g_mm_w - 1 DOWNTO (2*I + 1) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I)(g_count_w-1 DOWNTO g_mm_w), g_mm_w);  -- high part
     END GENERATE;
   END GENERATE;