Renamed ta2_unb2b_1GbE_mc to ta2_unb2b_1GbE

applications/ta2/ip/ta2_unb2b_1GbE_mc/hdllib.cfg → applications/ta2/ip/ta2_unb2b_1GbE/hdllib.cfg

-hdl_lib_name = ta2_unb2b_1GbE_mc
-hdl_library_clause_name = ta2_unb2b_1GbE_mc_lib
+hdl_lib_name = ta2_unb2b_1GbE
+hdl_library_clause_name = ta2_unb2b_1GbE_lib
 hdl_lib_uses_synth = common technology dp  
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 
 synth_files =
-  ta2_unb2b_1GbE_mc.vhd
+  ta2_unb2b_1GbE.vhd
 test_bench_files =     
 
 regression_test_vhdl = 

applications/ta2/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.tcl → applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl

-post_message "Running ta2_unb2b_1GbE_mc script"
+post_message "Running ta2_unb2b_1GbE script"
 set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
 #============================================================
 # Files and basic settings
 #============================================================
 
 # Local HDL files
-set_global_assignment -name VHDL_FILE ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
 
-# All used HDL library *_lib.qip files in order, copied from ta2_unb2b_1GbE_mc.qsf in RadioHDL build directory. 
+# All used HDL library *_lib.qip files in order, copied from ta2_unb2b_1GbE.qsf in RadioHDL build directory. 
 set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/technology/technology_lib.qip"
 set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_ram/ip_arria10_e1sg_ram_lib.qip"
 set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_memory/tech_memory_lib.qip"

applications/ta2/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd → applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd

@@ -50,7 +50,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 
-ENTITY ta2_unb2b_1GbE_mc IS       
+ENTITY ta2_unb2b_1GbE IS       
   PORT (      
     st_clk             : IN STD_LOGIC;
     st_rst             : IN STD_LOGIC;
@@ -69,10 +69,10 @@ ENTITY ta2_unb2b_1GbE_mc IS
     snk_out            : OUT t_dp_siso;
     snk_in             : IN  t_dp_sosi
   );
-END ta2_unb2b_1GbE_mc;
+END ta2_unb2b_1GbE;
 
 
-ARCHITECTURE str OF ta2_unb2b_1GbE_mc IS
+ARCHITECTURE str OF ta2_unb2b_1GbE IS
 
   CONSTANT c_sim                           : BOOLEAN := FALSE;
   CONSTANT c_empty_w                       : NATURAL := 2;

applications/ta2/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc_hw.tcl → applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_hw.tcl

@@ -4,7 +4,7 @@
 
 
 # 
-# ta2_unb2b_1GbE_mc "ta2_unb2b_1GbE_mc" v1.0
+# ta2_unb2b_1GbE "ta2_unb2b_1GbE" v1.0
 #  2020.01.28.08:39:40
 # 
 # 
@@ -16,15 +16,15 @@ package require -exact qsys 18.0
 
 
 # 
-# module ta2_unb2b_1GbE_mc
+# module ta2_unb2b_1GbE
 # 
 set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_1GbE_mc
+set_module_property NAME ta2_unb2b_1GbE
 set_module_property VERSION 1.0
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_1GbE_mc
+set_module_property DISPLAY_NAME ta2_unb2b_1GbE
 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 set_module_property EDITABLE true
 set_module_property REPORT_TO_TALKBACK false
@@ -36,10 +36,10 @@ set_module_property REPORT_HIERARCHY false
 # file sets
 # 
 add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_1GbE_mc_ip_wrapper
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_1GbE_ip_wrapper
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_1GbE_mc_ip_wrapper.vhd VHDL PATH ta2_unb2b_1GbE_mc_ip_wrapper.vhd TOP_LEVEL_FILE
+add_fileset_file ta2_unb2b_1GbE_ip_wrapper.vhd VHDL PATH ta2_unb2b_1GbE_ip_wrapper.vhd TOP_LEVEL_FILE
 
 
 # 

applications/ta2/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc_ip_wrapper.vhd → applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd

@@ -22,11 +22,11 @@
 -- Author:
 -- . Reinier van der Walle
 -- Purpose:
--- . Instantiates ta2_unb2b_1GbE_mc component 
+-- . Instantiates ta2_unb2b_1GbE component 
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 
-ENTITY ta2_unb2b_1GbE_mc_ip_wrapper IS       
+ENTITY ta2_unb2b_1GbE_ip_wrapper IS       
   PORT (      
     st_clk             : IN STD_LOGIC;
     st_rst             : IN STD_LOGIC;
@@ -59,14 +59,14 @@ ENTITY ta2_unb2b_1GbE_mc_ip_wrapper IS
     kernel_snk_valid   : IN  STD_LOGIC; -- TX data valid signal from kernel
     kernel_snk_ready   : OUT STD_LOGIC   -- Flow control towards kernel
   );
-END ta2_unb2b_1GbE_mc_ip_wrapper;
+END ta2_unb2b_1GbE_ip_wrapper;
 
 
-ARCHITECTURE str OF ta2_unb2b_1GbE_mc_ip_wrapper IS
+ARCHITECTURE str OF ta2_unb2b_1GbE_ip_wrapper IS
   ----------------------------------------------------------------------------
-  -- ta2_unb2b_1GbE_mc Component
+  -- ta2_unb2b_1GbE Component
   ----------------------------------------------------------------------------
-  COMPONENT ta2_unb2b_1GbE_mc IS
+  COMPONENT ta2_unb2b_1GbE IS
   PORT (
     st_clk             : IN STD_LOGIC;
     st_rst             : IN STD_LOGIC;
@@ -99,11 +99,11 @@ ARCHITECTURE str OF ta2_unb2b_1GbE_mc_ip_wrapper IS
     kernel_snk_valid   : IN  STD_LOGIC; -- TX data valid signal from kernel
     kernel_snk_ready   : OUT STD_LOGIC   -- Flow control towards kernel
   );
-  END COMPONENT ta2_unb2b_1GbE_mc;
+  END COMPONENT ta2_unb2b_1GbE;
 
 BEGIN
 
-  u_ta2_unb2b_1GbE_mc : ta2_unb2b_1GbE_mc 
+  u_ta2_unb2b_1GbE : ta2_unb2b_1GbE 
     PORT MAP (
       st_clk             => st_clk,
       st_rst             => st_rst,