Use standardized tb_tech_mac_10g* stimuli. Support g_nof_channels > 1.

libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd

@@ -26,11 +26,12 @@
 --   > as 5
 --   > run -all
 
-LIBRARY IEEE, technology_lib, tech_mac_10g_lib;
+LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
 USE IEEE.std_logic_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 USE tech_mac_10g_lib.tb_tech_mac_10g_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
 
 
 ENTITY tb_tb_tr_10GbE IS
@@ -38,22 +39,29 @@ END tb_tb_tr_10GbE;
 
 
 ARCHITECTURE tb OF tb_tb_tr_10GbE IS
-  CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'1');
-  SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(31 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
+  CONSTANT c_644       : TIME := tech_pll_clk_644_period;
+  CONSTANT c_156       : TIME := 6.4 ns;
+  CONSTANT c_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
+  
+  CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'1');
+  SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(7 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
 BEGIN
 
--- g_technology         : NATURAL := c_tech_stratixiv;
+-- g_technology              : NATURAL := c_tech_select_default;
 -- g_tb_end                  : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
--- g_sim_level          : NATURAL := 0;      -- 0 = use IP; 1 = use fast serdes model
 -- g_no_dut                  : BOOLEAN := FALSE;  -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
--- --   g_data_type = c_tb_tech_mac_10g_data_type_symbols  = 0
--- --   g_data_type = c_tb_tech_mac_10g_data_type_counter  = 1
--- g_data_type        : NATURAL := c_tb_tech_mac_10g_data_type_symbols
+-- g_sim_level               : NATURAL := 1;      -- 0 = use IP; 1 = use fast serdes model
+-- g_nof_channels            : NATURAL := 1;
+-- g_ref_clk_644_period      : TIME := tech_pll_clk_644_period;  -- for 10GBASE-R
+-- g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
+-- g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
+-- g_verify_link_recovery    : BOOLEAN := TRUE;
+-- g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11"
 
-  u_no_dut_counter                  : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0,  TRUE, c_tb_tech_mac_10g_data_type_counter) PORT MAP (tb_end_vec(0));
-  u_no_dut_symbols                  : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0,  TRUE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(1));
-  u_tr_10GbE_symbols                : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 0, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(5));
-  u_tr_10GbE_symbols_sim_level_is_1 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, 1, FALSE, c_tb_tech_mac_10g_data_type_symbols) PORT MAP (tb_end_vec(6));
+  u_no_dut                     : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE,  TRUE, 0, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(0));
+  u_tr_10GbE                   : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(1));
+  u_tr_10GbE_nof_channels_is_2 : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 0, 2, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(2));
+  u_tr_10GbE_sim_level_is_1    : ENTITY work.tb_tr_10GbE GENERIC MAP (c_tech_select_default, FALSE, FALSE, 1, 1, c_644, c_156, c_data_type, TRUE, "11") PORT MAP (tb_end_vec(3));
   
   p_tb_end : PROCESS
   BEGIN