Updated tr_10GbE port names. The tr_10GbE now uses tech_eth_10g.

boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd

@@ -794,8 +794,8 @@ BEGIN
       g_pkt_len       => c_def_10GbE_block_size
     )
     PORT MAP (
-      tr_clk_156          => SA_CLK,
-      tr_rst_156          => sa_rst,
+      tr_ref_clk_156      => SA_CLK,
+      tr_ref_rst_156      => sa_rst,
 
       cal_rec_clk         => cal_rec_clk, -- mm_clk, --cal_clk, mm_clk required by XAUI phy
 
@@ -820,12 +820,8 @@ BEGIN
       snk_in_arr          => dp_offload_tx_src_out_arr,
 
       -- Serial XAUI IO
-      xaui_tx_out_arr     => i_xaui_tx_arr,
-      xaui_rx_in_arr      => i_xaui_rx_arr,
-
-      -- Serial IO
-      serial_tx_out_arr   => OPEN,
-      serial_rx_in_arr    => (OTHERS => '0'),
+      xaui_tx_arr         => i_xaui_tx_arr,
+      xaui_rx_arr         => i_xaui_rx_arr,
 
       -- MDIO External clock and serial data.
       mdio_rst            => SI_FN_RSTN,