replace the two process approach (there is an issue that makes first data...

replace the two process approach (there is an issue that makes first data duplicate and last one missing) with a custume one

applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/pkg_signals.vhd

@@ -27,123 +27,128 @@ architecture BEHAVIOURAL of pkg_signals is
 
   signal sync_count : natural;
   signal sl_eop : std_logic;
-  signal sl_sop : std_logic;
+  signal sl_sop : std_logic;  
   
 	type state_type is (s_idle, s_count);
+	signal state       : state_type;
   
-  TYPE reg_type IS RECORD
-    write_in		: std_logic;
-		data_in 	  : std_logic_vector(31 downto 0);
-		control_in  : std_logic;    
-		sop         : std_logic;
-		eop         : std_logic;
-		sync_count  : natural;
-    state       : state_type;  -- The state machine. 
-  END RECORD;
+--  TYPE reg_type IS RECORD
+--   write_in		: std_logic;
+--		data_in 	  : std_logic_vector(31 downto 0);
+--		control_in  : std_logic;    
+--		sop         : std_logic;
+--		eop         : std_logic;
+--		sync_count  : natural;
+--    state       : state_type;  -- The state machine. 
+--  END RECORD;
 
-  SIGNAL r, rin      : reg_type;
+--SIGNAL r, rin      : reg_type;
 
 
 begin
  
---  sop_out <= sl_sop;
---  eop_out <= sl_eop;
---
---  pkg_signals_gen : PROCESS(CLK, RST, write_in)
---  begin
---    if rising_edge(CLK) then
---      if RST = '1' then
---        sl_sop <= '0';
---        sl_eop <= '0';
---        sync_state <= s_idle;
---        sync_count <= 0;
---      else
---        write_out <= write_in;
---        data_out <= data_in;
---        control_out <= control_in;
---        sync: case sync_state is
---          when s_idle => 
---            sl_sop <= write_in;
---            sl_eop <= '0';
---            if write_in = '1' then
---              sync_state <= s_count; 
---              sync_count <= 0;
---            end if;
---          when s_count =>    
---            sl_sop <= '0';
---            if write_in = '1' then
---							if sync_count < BLOCKS_PER_SYNC - 2 then
---								sync_count <= sync_count + 1;
---							else
---		            sl_eop <= '1';
---		            sync_state <= s_idle;
---		          end if;
---	          end if;
---	        when others =>
---	          sync_state <= s_idle;
---        end case;
---      end if;
---    end if;
---  end process;
-
-  p_comb : PROCESS(r, RST, write_in)
-    VARIABLE v : reg_type;
-  BEGIN
-   
-    v           := r;
-    
-    v.sop        := '0';  
-    v.eop        := '0';
-    v.write_in	 := write_in;		   
-    v.data_in 	 := data_in; 	  
-    v.control_in := control_in;  
-    
-    CASE r.state IS
-      WHEN s_idle => 
-        if write_in = '1' then    
-          v.sop   := '1';
-          v.state := s_count;  
-        END IF;
-
-      WHEN s_count =>  
-        if write_in = '1' then
-				  if r.sync_count < BLOCKS_PER_SYNC - 2 then
-					  v.sync_count := r.sync_count + 1;
-				  else
-		         v.eop := '1';
-		         v.state := s_idle;
-		         v.sync_count := 0;
-		       end if;
-        end if;
-      WHEN OTHERS =>
-        v.state := s_idle;
-
-    END CASE;
-    
-    IF(RST = '1') THEN 
-      v.sop        := '0';
-      v.eop        := '0';
-      v.state      := s_idle;
-      v.sync_count := 0;
-    END IF;
-
-    rin <= v;  
-         
-  END PROCESS;
-
-  p_regs : PROCESS(CLK)
-  BEGIN 
-    IF RISING_EDGE(CLK) THEN 
-      r <= rin; 
-    END IF; 
-  END PROCESS;
+  sop_out <= sl_sop;
+  eop_out <= sl_eop;
 
-  sop_out <= r.sop;
-  eop_out <= r.eop;
+  pkg_signals_gen : PROCESS(CLK, RST, write_in)
+  begin
+    if rising_edge(CLK) then
+      if RST = '1' then
+        sl_sop <= '0';
+        sl_eop <= '0';
+        state <= s_idle;
+        sync_count <= 0;
+      else
+        write_out <= write_in;
+        data_out <= data_in;
+        control_out <= control_in;
+        sync: case state is
+          when s_idle => 
+            sl_sop <= write_in;
+            sl_eop <= '0';
+            if write_in = '1' then
+              state <= s_count; 
+              sync_count <= 0;
+            end if;
+          when s_count =>    
+            sl_sop <= '0';
+            if write_in = '1' then
+							if sync_count < BLOCKS_PER_SYNC - 2 then
+								sync_count <= sync_count + 1;
+							else
+		            sl_eop <= '1';
+		            state <= s_idle;
+		          end if;
+	          end if;
+	        when others =>
+	          state <= s_idle;
+        end case;
+      end if;
+    end if;
+  end process;
 
-  write_out 	<= r.write_in;
-	data_out 	  <= r.data_in;
-	control_out <= r.control_in;
+-- there is an issue when using the two processes below
 
-end architecture;
+--  p_comb : PROCESS(r, RST, write_in)
+--    VARIABLE v : reg_type;
+--  BEGIN
+--   
+--    v           := r;
+--    
+--    v.sop        := '0';  
+--    v.eop        := '0';
+--    v.write_in	 := write_in;		   
+--    v.data_in 	 := data_in; 	  
+--    v.control_in := control_in;  
+--    
+--    CASE v.state IS
+--      WHEN s_idle => 
+--        if write_in = '1' then    
+--          v.sop   := '1';
+--          v.state := s_count;  
+--        END IF;
+--
+--      WHEN s_count =>  
+--        if write_in = '1' then
+--				  if r.sync_count < BLOCKS_PER_SYNC - 2 then
+--					  v.sync_count := r.sync_count + 1;
+--				  else
+--		         v.eop := '1';
+--		         v.state := s_idle;
+--		         v.sync_count := 0;
+--		       end if;
+--        end if;
+--      WHEN OTHERS =>
+--        v.state := s_idle;
+--
+--    END CASE;
+--    
+--    IF(RST = '1') THEN 
+--      v.sop        := '0';
+--      v.eop        := '0';
+--      v.state      := s_idle;
+--      v.sync_count := 0;
+--      v.data_in    := (others => '0');
+--      v.write_in   := '0';
+--      v.control_in   := '0';      
+--    END IF;
+--
+--    rin <= v;  
+--         
+--  END PROCESS;
+--
+--  p_regs : PROCESS(CLK)
+--  BEGIN 
+--    IF RISING_EDGE(CLK) THEN 
+--      r <= rin; 
+--    END IF; 
+--  END PROCESS;
+--
+--  sop_out <= r.sop;
+--  eop_out <= r.eop;
+--
+--  data_out    <= r.data_in;
+--  write_out 	<= r.write_in;
+--	control_out <= r.control_in;
 
+end architecture;                                                           
\ No newline at end of file