Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key...

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

applications/apertif/apertif_unb1_correlator/hdllib.cfg

 hdl_lib_name = apertif_unb1_correlator
 hdl_library_clause_name = apertif_unb1_correlator_lib
-hdl_lib_uses = common mm dp i2c unb1_board correlator diag rTwoSDF wpfb st filter fft
+hdl_lib_uses_synth = common mm dp i2c unb1_board correlator diag rTwoSDF wpfb st filter fft
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

applications/unb1_fn_bf/hdllib.cfg

 hdl_lib_name = unb1_fn_bf
 hdl_library_clause_name = unb1_fn_bf_lib
-hdl_lib_uses = common technology mm i2c unb1_board bf
+hdl_lib_uses_synth = common technology mm i2c unb1_board bf
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

 hdl_lib_name = unb1_ddr3
 hdl_library_clause_name = unb1_ddr3_lib
-hdl_lib_uses = common mm i2c unb1_board dp eth diagnostics ddr3
+hdl_lib_uses_synth = common mm i2c unb1_board dp eth diagnostics ddr3
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_minimal/hdllib.cfg

 hdl_lib_name = unb1_minimal
 hdl_library_clause_name = unb1_minimal_lib
-hdl_lib_uses = common mm unb1_board 
+hdl_lib_uses_synth = common mm unb1_board 
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg

 hdl_lib_name = unb1_minimal_qsys
 hdl_library_clause_name = unb1_minimal_qsys_lib
-hdl_lib_uses = unb1_board unb1_minimal
+hdl_lib_uses_synth = unb1_board unb1_minimal
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg

 hdl_lib_name = unb1_minimal_sopc
 hdl_library_clause_name = unb1_minimal_sopc_lib
-hdl_lib_uses = unb1_board unb1_minimal
+hdl_lib_uses_synth = unb1_board unb1_minimal
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_test/hdllib.cfg

 hdl_lib_name = unb1_test
 hdl_library_clause_name = unb1_test_lib
-hdl_lib_uses = common technology mm unb1_board dp eth tech_tse tr_10GbE mdio diagnostics diag
+hdl_lib_uses_synth = common technology mm unb1_board dp eth tech_tse tr_10GbE mdio diagnostics diag
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg

 hdl_lib_name = unb1_test_10GbE
 hdl_library_clause_name = unb1_test_10GbE_lib
-hdl_lib_uses = unb1_board unb1_test
+hdl_lib_uses_synth = unb1_board unb1_test
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg

 hdl_lib_name = unb1_test_lpbk
 hdl_library_clause_name = unb1_test_lpbk_lib
-hdl_lib_uses = unb1_board unb1_test
+hdl_lib_uses_synth = unb1_board unb1_test
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg

 hdl_lib_name = unb1_test_qsys
 hdl_library_clause_name = unb1_test_qsys_lib
-hdl_lib_uses = unb1_board unb1_test
+hdl_lib_uses_synth = unb1_board unb1_test
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg

 hdl_lib_name = unb1_tr_10GbE
 hdl_library_clause_name = unb1_tr_10GbE_lib
-hdl_lib_uses = common mm i2c unb1_board dp eth tr_xaui tr_10GbE mdio diagnostics
+hdl_lib_uses_synth = common mm i2c unb1_board dp eth tr_xaui tr_10GbE mdio diagnostics
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard1/libraries/unb1_board/hdllib.cfg

 hdl_lib_name = unb1_board
 hdl_library_clause_name = unb1_board_lib
-hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
+hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_stratixiv
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard2/designs/unb2_minimal/hdllib.cfg

 hdl_lib_name = unb2_minimal
 hdl_library_clause_name = unb2_minimal_lib
-hdl_lib_uses = common technology mm unb2_board 
+hdl_lib_uses_synth = common technology mm unb2_board 
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_arria10
 
 build_dir_sim = $HDL_BUILD_DIR

boards/uniboard2/designs/unb2_test/hdllib.cfg

 hdl_lib_name = unb2_test
 hdl_library_clause_name = unb2_test_lib
-hdl_lib_uses = common technology mm unb2_board dp eth tech_tse tr_10GbE diagnostics diag
+hdl_lib_uses_synth = common technology mm unb2_board dp eth tech_tse tr_10GbE diagnostics diag
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_arria10
 
 

boards/uniboard2/libraries/unb2_board/hdllib.cfg

 hdl_lib_name = unb2_board
 hdl_library_clause_name = unb2_board_lib
-hdl_lib_uses = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs tr_10GbE
+hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technology tech_pll epcs tr_10GbE
+hdl_lib_uses_sim = 
+
 hdl_lib_technology = ip_arria10
 
 build_dir_sim = $HDL_BUILD_DIR