Merge branch 'RTSD-229' into 'master'

RTSD-229: Verify the wpfb for iwave agilex7 through synthesis in Quartus

Closes RTSD-229

See merge request !370

libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd

@@ -50,15 +50,15 @@ use mm_lib.mm_file_pkg.all;
 use dp_lib.dp_stream_pkg.all;
 use work.diag_pkg.all;
 
-entity tb_diag_data_buffer is
+entity tb_diag_data_buffer_dev is
   generic(
     g_nof_streams : positive :=  2;  -- = 16
     g_nof_data    : positive := 128;
     g_data_w      : positive :=  16  -- = 16
   );
-end tb_diag_data_buffer;
+end tb_diag_data_buffer_dev;
 
-architecture tb of tb_diag_data_buffer is
+architecture tb of tb_diag_data_buffer_dev is
   constant c_sim                : boolean := true;
 
   ----------------------------------------------------------------------------
@@ -257,7 +257,7 @@ begin
   ----------------------------------------------------------------------------
   -- DUT: Device Under Test
   ----------------------------------------------------------------------------
-  u_dut : entity work.mms_diag_data_buffer
+  u_dut : entity work.mms_diag_data_buffer_dev
   generic map (
     g_nof_streams     => c_db_nof_streams,
     g_data_type       => c_db_data_type_re,

libraries/dsp/wpfb/quartus_iwave/README.txt

+###############################################################################
+# 
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+###############################################################################
+
+
+README.txt for $HDL_WORK/libraries/dsp/wpfb/quartus_iwave
+VERSION 01 - 20231219
+
+Contents:
+
+1) Purpose
+2) Description
+3) Parameters (ALMA vs LOFAR2)
+4) Synthesis
+5) Agilex7 issues
+6) References
+
+
+
+1) Purpose
+
+  To investigate the resource usage, timing reports with fmax summary and time critical
+  paths by synthesis of the Subband Filterbank (wpfb_unit_dev.vhd) for the Agilex 7
+  (agi027_xxxx) FPGA with buildset iwave.
+
+
+2) Description 
+
+  The synthesis is the second step to verify the correct working and limits of the wpfb
+  and underlying designs and libraries for this new FPGA. Therefore all the FPGA specific
+  components (IPs) are ported and sometimes an implementation is made to still be able to
+  use the generic designs for this and all other FPGA types. 
+
+  I created a Quartus project wpfb_unit_dev.qpf and qsf with the QUI that gets copied into
+  build/iwave/quartus/iwave_synthesis_wpfb_lofar2/iwave_synthesis_wpfb_lofar2.qpf by
+  the quartus_iwave/lofar2/hdllib.cfg.
+  The wpfb_unit_dev component has too many IO to fit on the FPGA.
+  Therefore it is necessary to use virtual pins, as explained in [1]. No separate
+  After doing doing 'quartus_config iwave', then the iwave_synthesis_wpfb_lofar2.qpf
+  (or .qsf) in the build dir can be opened in the QUI (started via run_quartus iwave &)
+  and then do 'Start compilation'.
+
+
+3) Parameters (ALMA vs LOFAR2)
+
+  It is preferable to make a distinction between the selected parameters (ALMA vs LOFAR2).
+  Normally with applications we will use revisions and a separate quartus folder.
+  But when a synthesis folder is made for a particularly design, almost all the time the
+  foldername is quartus or quartus_<buildset>. So this is the reason I made a distinction
+  between alma and lofar2 in the quartus_iwave folder.
+
+  . iwave_synthesis_wpfb_lofar2.vhd:
+    synthesis compilation has runned with this design as top-level entity.
+
+  . iwave_synthesis_wpfb_alma.vhd:
+    The design for ALMA is already there. Intended to be a top-level entity for synthesis with
+    ALMA parameters. Currently the same as LOFAR2. Therefore I added it with multiple comments
+    with which parameters have to be changed when the ALMA parameters are determined.
+
+
+4) Synthesis
+
+ a) Results
+  
+    The Design Documentation can be found on Confluence [2].
+
+    Important synthesis results are in the Design Assistant report. In the directionary it can be found
+    under: $HDL_BUILD/iwave/quartus/iwave_synthesis_wpfb_lofar2/output_files/iwave_synthesis_wpfb_lofar2
+      .fit.place.rpt    or
+      .fit.finalize.rpt         ->  for resource usage
+      .drc.partitioned.rpt      ->  for severity failures
+      .tq.drc.signoff.rpt       ->  for timing analyzer
+
+    It also can be found when running via QUI under:
+      .  Fitter > Place Stage > Resource Usage Summary (/ Resource Utilazation by Entity) -> Resource usage
+      .  Timing Analyzer > Fmax Summary                                                   -> Maximum Fclk due to timing path 
+      .  Timing Analyzer > Worst-Case Timing Paths > Setup > (dp_clk or mm_clk)           -> Timing critical paths
+
+    The most important information from these reports of WPFB implementation synthesis results with the 
+    LOFAR2 parameters can be found on Confluence, see [3].
+
+    The synthesis of the WPFB with the ALMA design parameters still needs to be done. Therefore this system-
+    parameters must be determined, changed and included in the top-level entity design.
+
+ b) How-to-do with QUI
+  
+    . Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
+    . QUI is the Quartus GUI. Run this software by the terminal command run_quartus <buildset> 
+    . Open the project (.qpf or .qsf) in the $HDL_BUILD/iwave/quartus/iwave_synthesis_wpfb_lofar2 folder
+    . by redo 'Start compilation'. After this compilation has ended open the fitter report with the QUI
+      or in the outpul_files.
+
+ c) How-to-do with terminal command using the ARGS Tooling (git repository)
+
+    . Use the terminal command quartus_config <buildset> to create/update all the projectfiles for iwave.
+    . Make sure numpy is installed.
+    . Use the terminal command build_image <buildset> <project_design> <options --rev=<revision-to-use> 
+      --seed=<seed(s)-to-use-for-fitting>>
+      to run the complete synthesis. Such as: build_image unb2c unb2c_test --rev=unb2c_test_minimal
+    . Use the next terminal commands to run parts of the the build_image command separately,
+      that are needed by the synthesis:
+      . Use the terminal command gen_rom_mmap.py --avalon -d <project_design> -r <revision-to-use>
+        to generate fpgamap.py M&C Python client include file.
+        Add flag --avalon to use config file qsys/sopc for base addresses.
+        Such as: gen_rom_mmap.py --avalon -d unb2c_test -r unb2c_test_minimal
+      . Use the terminal command run_qcomp <buildset> <project_design> <options --rev --clk --seed --32bit>
+        to create the registermap for the buildset.
+        Such as: run_qcomp unb2c unb2c_test_minimal
+      . Use the terminal command run_rbf buildset> <project_design> <options --rev>
+        Such as: run_rbf unb2c unb2c_test_minimal
+  
+
+5) Agilex7 issues
+
+  Important crictical warnings:
+  . Critical Warning(20759):  Use the Reset Release IP in Intel Agilex 7 FPGA designs to ensure a successful configuration.
+                              For more information about the Reset Release IP, refer to the Intel Agilex Configuration User Guide. 
+    FW engineer comment:      The Reset Release Intel FPGA IP available in the Intel Quartus Prime Pro software is necessary to use
+                              in all Intel Agilex devices to hold your design in reset until the FPGA has finished with the
+                              configuration process. This means for us that the Reset Release IP must be implemented in the BSP
+                              (Board Support Package). See [4] and [5].
+
+  Inimportant crictical warnings:
+  . Critical Warning(332012): Synopsys Design Constraints File file not found: 'iwave_synthesis_wpfb_lofar2.sdc'.
+                              A Synopsys Design Constraints File is required by the Timing Analyzer to get proper
+                              timing constraints. Without it, the Compiler will not properly optimize the design. 
+  . Critical Warning(19317):  No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" 
+  . Critical Warning(332148): Timing requirements not met 
+    FW engineer comment:      No need to a sdc file because default clock by Quartus is 1 GHz for finding Fmax.
+
+  . Critical Warning(12677):  No exact pin location assignment(s) for 2 pins of 2 total pins.
+                              For the list of pins please refer to the I/O Assignment Warnings table in the fitter report 
+    FW engineer comment:      The two clock pins (dp_clock and mm_clock) are not assigned to virtual pins (commented out),
+                              but Quartus will self specifies the fitter assigned location.
+                              Refer Assignments > Pin Planner in Quartus to see tis locations.
+
+  . Critical Warning(18636):  Compilation Report contains advance information. Specifications for device 
+                              AGIB027R31A1I1VB are subject to change. Contact Intel for information on availability.
+                              No programming file will be generated. 
+    FW engineer comment:      The selected device part is for configuration is AGIB027R31A1I1VB, because the real 
+                              device part is unknown until delivery. It is likely that the selected part, used 
+                              for configuration, is not currently in production, and this inference can be drawn
+                              from the presence of the warning.
+
+  . Solutions to solved Critical Warnings and Errors are described in the qsf file.
+
+
+6) References:
+
+ [1] "Virtual Pin Assignments in a Partial Design", Apr 17, 2021,
+     https://www.youtube.com/watch?v=QET0lC-jdAQ
+ [2] "Synthesis of the wpfb_unit_dev with quartus_iwave", Dec 18, 2023,
+     https://support.astron.nl/confluence/display/SBe/FW+Design+Document%3A+Synthesis+of+the+wpfb_unit_dev+with+quartus_iwave
+ [3] "Subband Filterbank = wpfb synthesis results iwave Agilex7", Dec 19, 2023,
+     https://support.astron.nl/confluence/display/SBe/Subband+Filterbank+%3D+wpfb+synthesis+results+iwave+Agilex7s
+ [4] "File: ug-ag-config-683673-777132-1.pdf; AN 891: Using the Reset Release Intel FPGA IP - User Guide", Sept 30, 2019 
+     https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/archives/an891-19-3.pdf
+     See Reset Release Chapter 4.3. Gating the PLL Reset Signal
+ [5] "An Essential Reset for Intel® Stratix® 10 & Intel Agilex™ Devices", Jun 28, 2021
+     https://www.youtube.com/watch?v=qhGfZwX9jKw

libraries/dsp/wpfb/quartus_iwave/alma/hdllib.cfg

+hdl_lib_name = iwave_synthesis_wpfb_alma
+hdl_library_clause_name = iwave_synthesis_wpfb_alma_lib
+hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files = 
+    iwave_synthesis_wpfb_alma.vhd
+  
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+quartus_copy_files =
+    # Note: path $HDL_WORK is equivalent to relative path ../../../../../
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+
+synth_top_level_entity = 
+    iwave_synthesis_wpfb_alma
+
+# use qsf also for (virtual) pin assignments, no separate tcl file is needed
+quartus_qsf_files =
+    $HDL_WORK/libraries/dsp/wpfb/quartus_iwave/wpfb_unit_dev.qsf
+
+# use no sdc file because default clock by Quartus is 1 GHz for finding Fmax.
+quartus_sdc_files =

libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- #TODO: Change to ALMA Design parameters: two ?? (TBD)
+-- Author:
+-- . D.F. Brouwer
+-- Design name:
+-- . iwave_synthesis_wpfb_alma
+-- Purpose:
+-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband 
+--   statistics and streaming interfaces) synthesis design for iwave Agilex 7
+--   (c_tech_agi027_xxxx).
+-- . Implements the functionality of the subband filterbank (Fsub) using the 
+--   ALMA design parameters. 
+-- Description:
+-- . The subband filterbank seperates the incoming timestamped ADC samples into
+--   ?? (TBD) frequency bands called subbands.
+-- . It implements a critically sampled poly-phase filterbank (PFB). The PFB
+--   consists of a poly-phase finite impulse response (PFIR) filter per real
+--   input and a complex fast fourier transform (FFT) per 2 real inputs.
+-- . The number of points of the FFT is ?? (TBD).
+-- Description:
+-- . The quantized subbands are output (and used for the SST) because it uses more logic.
+--    ____ 
+--   |    |
+--   |    |--raw----> X (not included in synthesis)
+--   |WPFB|
+--   |    |--quant--> wpfb_unit_out_quant_sosi_arr (more logic = critical timepath is longer)
+--   |____|
+
+library IEEE, common_lib, dp_lib, rTwoSDF_lib, common_mult_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
+use IEEE.std_logic_1164.all;
+use common_lib.common_pkg.all;
+use common_lib.common_mem_pkg.all;
+use dp_lib.dp_stream_pkg.all;
+use rTwoSDF_lib.rTwoSDFPkg.all;
+use filter_lib.fil_pkg.all;
+use fft_lib.fft_pkg.all;
+use wpfb_lib.wpfb_pkg.all;
+
+entity iwave_synthesis_wpfb_alma is
+  generic (
+    g_wpfb                       : t_wpfb  := c_wpfb_lofar2_subbands_l2ts_18b; -- Instance of the wpfb type (t_wpfb) which is the same config as defined in c_sdp_wpfb_subbands #TODO: Change to ALMA Design parameters
+    g_nof_streams                : natural := 12   -- Number of signals per processing node #TODO: Change to ALMA Design parameters
+  );
+  port (
+    dp_clk                       : in  std_logic;  -- Same clock, reset for dp as for mm, because of compatibility of Agilex 7.
+    dp_rst                       : in  std_logic;  -- ,, ,,
+    mm_clk                       : in  std_logic;  -- ,, ,,
+    mm_rst                       : in  std_logic;  -- ,, ,,
+    reg_si_copi                  : in  t_mem_copi := c_mem_copi_rst;
+    reg_si_cipo                  : out t_mem_cipo;
+    ram_fil_coefs_copi           : in  t_mem_copi := c_mem_copi_rst;
+    ram_fil_coefs_cipo           : out t_mem_cipo;
+    ram_st_sst_copi              : in  t_mem_copi := c_mem_copi_rst;  -- Subband statistics registers
+    ram_st_sst_cipo              : out t_mem_cipo;
+    in_sosi_arr                  : in  t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+    out_quant_sosi_arr           : out t_dp_sosi_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0)
+  );
+end iwave_synthesis_wpfb_alma;
+
+architecture str of iwave_synthesis_wpfb_alma is
+  -- FIR coeffs file is copied to build data/ dir by design revision hdllib.cfg
+  -- from: $HDL_WORK/libraries/dsp/filter/src/hex
+  constant c_coefs_file_prefix        : string := "data/Coeffs16384Kaiser-quant_1wb"; --#TODO: Check and if needed change to ALMA Design parameters
+
+  constant c_nof_pfb                  : natural := g_wpfb.nof_wb_streams * g_wpfb.wb_factor; -- Default 6 PFB units, is 6 signal output pairs #TODO: Change to ALMA Design parameters
+  constant c_in_dat_w                 : natural := g_wpfb.fil_in_dat_w; -- Default number of input bits of the ADC is 14 #TODO: Change to ALMA Design parameters
+
+  constant c_si_pipeline              : natural := 1;
+
+  signal si_sosi_arr                  : t_dp_sosi_arr(g_nof_streams - 1 downto 0)  := (others => c_dp_sosi_rst);
+
+  signal wpfb_unit_in_sosi_arr        : t_dp_sosi_arr(c_nof_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+  signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_nof_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+begin
+  ---------------------------------------------------------------
+  -- SPECTRAL INVERSION
+  ---------------------------------------------------------------
+  u_si_arr : entity si_lib.si_arr
+  generic map (
+    g_nof_streams => g_nof_streams,
+    g_pipeline    => c_si_pipeline,
+    g_dat_w       => c_in_dat_w
+  )
+  port map(
+    in_sosi_arr  => in_sosi_arr,
+    out_sosi_arr => si_sosi_arr,
+
+    reg_si_mosi  => reg_si_copi,
+    reg_si_miso  => reg_si_cipo,
+
+    mm_rst       => mm_rst,
+    mm_clk       => mm_clk,
+    dp_clk       => dp_clk,
+    dp_rst       => dp_rst
+  );
+
+  ---------------------------------------------------------------
+  -- POLY-PHASE FILTERBANK
+  ---------------------------------------------------------------
+  -- Connect the 12 ADC streams to the re and im fields of the PFB input. #TODO: Change to ALMA Design parameters
+  p_pfb_streams : process(si_sosi_arr)
+  begin
+    for I in 0 to c_nof_pfb - 1 loop
+      wpfb_unit_in_sosi_arr(I) <= si_sosi_arr(2 * I);
+      wpfb_unit_in_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(si_sosi_arr(2 * I).data);
+      wpfb_unit_in_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(si_sosi_arr(2 * I + 1).data);
+    end loop;
+  end process;
+
+  -- PFB
+  u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
+  generic map (
+    g_wpfb                => g_wpfb,
+    g_use_prefilter       => true,
+    g_stats_ena           => false,               -- Enables the statistics unit. For wpfb_unit_dev default true
+    g_use_bg              => false,
+    g_coefs_file_prefix   => c_coefs_file_prefix, -- File prefix for the coefficients files. For wpfb_unit_dev default "data/coefs_wide"
+    g_restart_on_valid    => false                -- For wpfb_unit_dev default true
+  )
+  port map (
+    dp_rst                => dp_rst,
+    dp_clk                => dp_clk,
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+
+    ram_fil_coefs_mosi    => ram_fil_coefs_copi,
+    ram_fil_coefs_miso    => ram_fil_coefs_cipo,
+    ram_st_sst_mosi       => ram_st_sst_copi,     -- Subband statistics registers
+    ram_st_sst_miso       => ram_st_sst_cipo,
+    in_sosi_arr           => wpfb_unit_in_sosi_arr,
+    out_quant_sosi_arr    => wpfb_unit_out_quant_sosi_arr
+  );
+
+  out_quant_sosi_arr <= wpfb_unit_out_quant_sosi_arr;
+
+end str;

libraries/dsp/wpfb/quartus_iwave/lofar2/hdllib.cfg

+hdl_lib_name = iwave_synthesis_wpfb_lofar2
+hdl_library_clause_name = iwave_synthesis_wpfb_lofar2_lib
+hdl_lib_uses_synth = common diag dp fft filter mm pft2 pfb2 rTwoSDF si st wpfb
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files = 
+    iwave_synthesis_wpfb_lofar2.vhd
+  
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+quartus_copy_files =
+    # Note: path $HDL_WORK is equivalent to relative path ../../../../../
+    $HDL_WORK/libraries/dsp/filter/src/hex  data   # FIR filter coefficients
+
+synth_top_level_entity = 
+    iwave_synthesis_wpfb_lofar2
+
+# use qsf also for (virtual) pin assignments, no separate tcl file is needed
+quartus_qsf_files =
+    $HDL_WORK/libraries/dsp/wpfb/quartus_iwave/wpfb_unit_dev.qsf
+
+# use no sdc file because default clock by Quartus is 1 GHz for finding Fmax.
+quartus_sdc_files =

libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author:
+-- . D.F. Brouwer
+-- Design name:
+-- . iwave_synthesis_wpfb_lofar2
+-- Purpose:
+-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband 
+--   statistics and streaming interfaces) synthesis design for iwave Agilex 7
+--   (c_tech_agi027_xxxx).
+-- . Implements the functionality of the subband filterbank (Fsub) using the 
+--   LOFAR2 design parameters. 
+-- Description:
+-- . The subband filterbank seperates the incoming timestamped ADC samples into
+--   512 frequency bands called subbands.
+-- . It implements a critically sampled poly-phase filterbank (PFB). The PFB
+--   consists of a poly-phase finite impulse response (PFIR) filter per real
+--   input and a complex fast fourier transform (FFT) per 2 real inputs.
+-- . The number of points of the FFT is 1024.
+-- Description:
+-- . The quantized subbands are output (and used for the SST) because it uses more logic.
+--    ____ 
+--   |    |
+--   |    |--raw----> X (not included in synthesis)
+--   |WPFB|
+--   |    |--quant--> wpfb_unit_out_quant_sosi_arr (more logic = critical timepath is longer)
+--   |____|
+
+library IEEE, common_lib, dp_lib, rTwoSDF_lib, common_mult_lib, fft_lib, wpfb_lib, filter_lib, si_lib, st_lib, mm_lib;
+use IEEE.std_logic_1164.all;
+use common_lib.common_pkg.all;
+use common_lib.common_mem_pkg.all;
+use dp_lib.dp_stream_pkg.all;
+use rTwoSDF_lib.rTwoSDFPkg.all;
+use filter_lib.fil_pkg.all;
+use fft_lib.fft_pkg.all;
+use wpfb_lib.wpfb_pkg.all;
+
+entity iwave_synthesis_wpfb_lofar2 is
+  generic (
+    g_wpfb                       : t_wpfb  := c_wpfb_lofar2_subbands_l2ts_18b; -- Instance of the wpfb type (t_wpfb) which is the same config as defined in c_sdp_wpfb_subbands
+    g_nof_streams                : natural := 12   -- Number of signals per processing node
+  );
+  port (
+    dp_clk                       : in  std_logic;  -- Same clock, reset for dp as for mm, because of compatibility of Agilex 7.
+    dp_rst                       : in  std_logic;  -- ,, ,,
+    mm_clk                       : in  std_logic;  -- ,, ,,
+    mm_rst                       : in  std_logic;  -- ,, ,,
+    reg_si_copi                  : in  t_mem_copi := c_mem_copi_rst;
+    reg_si_cipo                  : out t_mem_cipo;
+    ram_fil_coefs_copi           : in  t_mem_copi := c_mem_copi_rst;
+    ram_fil_coefs_cipo           : out t_mem_cipo;
+    ram_st_sst_copi              : in  t_mem_copi := c_mem_copi_rst;  -- Subband statistics registers
+    ram_st_sst_cipo              : out t_mem_cipo;
+    in_sosi_arr                  : in  t_dp_sosi_arr(g_nof_streams - 1 downto 0);
+    out_quant_sosi_arr           : out t_dp_sosi_arr(g_wpfb.nof_wb_streams * g_wpfb.wb_factor - 1 downto 0)
+  );
+end iwave_synthesis_wpfb_lofar2;
+
+architecture str of iwave_synthesis_wpfb_lofar2 is
+  -- FIR coeffs file is copied to build data/ dir by design revision hdllib.cfg
+  -- from: $HDL_WORK/libraries/dsp/filter/src/hex
+  constant c_coefs_file_prefix        : string := "data/Coeffs16384Kaiser-quant_1wb";
+
+  constant c_nof_pfb                  : natural := g_wpfb.nof_wb_streams * g_wpfb.wb_factor; -- Default 6 PFB units, is 6 signal output pairs
+  constant c_in_dat_w                 : natural := g_wpfb.fil_in_dat_w; -- Default number of input bits of the ADC is 14
+
+  constant c_si_pipeline              : natural := 1;
+
+  signal si_sosi_arr                  : t_dp_sosi_arr(g_nof_streams - 1 downto 0)  := (others => c_dp_sosi_rst);
+
+  signal wpfb_unit_in_sosi_arr        : t_dp_sosi_arr(c_nof_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+  signal wpfb_unit_out_quant_sosi_arr : t_dp_sosi_arr(c_nof_pfb - 1 downto 0) := (others => c_dp_sosi_rst);
+
+begin
+  ---------------------------------------------------------------
+  -- SPECTRAL INVERSION
+  ---------------------------------------------------------------
+  u_si_arr : entity si_lib.si_arr
+  generic map (
+    g_nof_streams => g_nof_streams,
+    g_pipeline    => c_si_pipeline,
+    g_dat_w       => c_in_dat_w
+  )
+  port map(
+    in_sosi_arr  => in_sosi_arr,
+    out_sosi_arr => si_sosi_arr,
+
+    reg_si_mosi  => reg_si_copi,
+    reg_si_miso  => reg_si_cipo,
+
+    mm_rst       => mm_rst,
+    mm_clk       => mm_clk,
+    dp_clk       => dp_clk,
+    dp_rst       => dp_rst
+  );
+
+  ---------------------------------------------------------------
+  -- POLY-PHASE FILTERBANK
+  ---------------------------------------------------------------
+  -- Connect the 12 ADC streams to the re and im fields of the PFB input.
+  p_pfb_streams : process(si_sosi_arr)
+  begin
+    for I in 0 to c_nof_pfb - 1 loop
+      wpfb_unit_in_sosi_arr(I) <= si_sosi_arr(2 * I);
+      wpfb_unit_in_sosi_arr(I).re <= RESIZE_DP_DSP_DATA(si_sosi_arr(2 * I).data);
+      wpfb_unit_in_sosi_arr(I).im <= RESIZE_DP_DSP_DATA(si_sosi_arr(2 * I + 1).data);
+    end loop;
+  end process;
+
+  -- PFB
+  u_wpfb_unit_dev : entity wpfb_lib.wpfb_unit_dev
+  generic map (
+    g_wpfb                => g_wpfb,
+    g_use_prefilter       => true,
+    g_stats_ena           => false,               -- Enables the statistics unit. For wpfb_unit_dev default true
+    g_use_bg              => false,
+    g_coefs_file_prefix   => c_coefs_file_prefix, -- File prefix for the coefficients files. For wpfb_unit_dev default "data/coefs_wide"
+    g_restart_on_valid    => false                -- For wpfb_unit_dev default true
+  )
+  port map (
+    dp_rst                => dp_rst,
+    dp_clk                => dp_clk,
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+
+    ram_fil_coefs_mosi    => ram_fil_coefs_copi,
+    ram_fil_coefs_miso    => ram_fil_coefs_cipo,
+    ram_st_sst_mosi       => ram_st_sst_copi,     -- Subband statistics registers
+    ram_st_sst_miso       => ram_st_sst_cipo,
+    in_sosi_arr           => wpfb_unit_in_sosi_arr,
+    out_quant_sosi_arr    => wpfb_unit_out_quant_sosi_arr
+  );
+
+  out_quant_sosi_arr <= wpfb_unit_out_quant_sosi_arr;
+
+end str;

libraries/dsp/wpfb/quartus_iwave/wpfb_unit_dev.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 23.2.0 Build 94 06/14/2023 SC Pro Edition
+# Date created = 15:10:36  November 24, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "23.2"
+DATE = "15:10:36  November 24, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "wpfb_unit_dev"

libraries/dsp/wpfb/quartus_iwave/wpfb_unit_dev.qsf

+###############################################################################
+# 
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+###############################################################################
+# 
+# Author: 
+# . D.F. Brouwer, 24 November 2023
+# Purpose: 
+# . Synthesis of wpfb_unit_dev to investigate resource usages, timing reports 
+#   with fmax summary and time critical paths.
+# Description:
+# . Created wpfb_unit_dev.qpf and qsf with QUI using run_quartus iwave &
+# . Used virtual pins so that it fits the FPGA, as explained in [1].
+# References:
+# [1] "Virtual Pin Assignments in a Partial Design", Apr 17, 2021,
+#     https://www.youtube.com/watch?v=QET0lC-jdAQ
+
+set_global_assignment -name LAST_QUARTUS_VERSION "23.2.0 Pro Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name DEVICE AGIB027R31A1I1VB
+set_global_assignment -name FAMILY "Agilex 7"
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+
+# Due to " critical warning(19238): Incomplete power management setting .."
+# and the specified missing required settings used QUI to add this settings
+# Quartus Prime Pro->Assignments->Device->Device and Pin Option...->
+# (Configuration->Configuration pin options)/(Power managements ).
+set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
+set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
+# (Power Management & VID).
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F
+
+
+# Used QUI to add the ports of iwave_synthesis_wpfb with underlying 
+# wpfb_unit_dev as virtual pins so that it fits the FPGA [1].
+set_instance_assignment -name VIRTUAL_PIN ON -to dp_rst
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].valid
+#set_instance_assignment -name VIRTUAL_PIN ON -to mm_clk
+set_instance_assignment -name VIRTUAL_PIN ON -to mm_rst
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].eop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].sop
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].sync
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].valid
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_cipo.rdval
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_cipo.waitrequest
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_copi.rd
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_copi.wr
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_cipo.rdval
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_cipo.waitrequest
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_copi.rd
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_copi.wr
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_cipo.rdval
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_cipo.waitrequest
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_copi.rd
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_copi.wr
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[0].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[1].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[2].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[3].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[4].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[5].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[6].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[7].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[8].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[9].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[10].re
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].data
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].err
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].im
+set_instance_assignment -name VIRTUAL_PIN ON -to in_sosi_arr[11].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[0].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[1].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[2].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[3].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[4].re
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].bsn
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].channel
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].data
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].empty
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].err
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].im
+set_instance_assignment -name VIRTUAL_PIN ON -to out_quant_sosi_arr[5].re
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_cipo.rddata
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_copi.address
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_fil_coefs_copi.wrdata
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_cipo.rddata
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_copi.address
+set_instance_assignment -name VIRTUAL_PIN ON -to ram_st_sst_copi.wrdata
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_cipo.rddata
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_copi.address
+set_instance_assignment -name VIRTUAL_PIN ON -to reg_si_copi.wrdata
+#set_instance_assignment -name VIRTUAL_PIN ON -to dp_clk

libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd

@@ -37,7 +37,7 @@ use ieee.numeric_std.all;
 library lpm;
 use lpm.lpm_components.all;
 
- entity  ip_agi027_xxxx_mult is
+ entity ip_agi027_xxxx_mult is
   generic (
     g_in_a_w           : positive := 18;  -- Width of the data A port
     g_in_b_w           : positive := 18;  -- Width of the data B port
@@ -80,7 +80,7 @@ architecture str of ip_agi027_xxxx_mult is
   );
   port (
       dataa : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
-      datab : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+      datab : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
     --  sum : in STD_LOGIC_VECTOR((g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
     --  aclr : in STD_LOGIC; (not used in current designs)
       clock : in std_logic;

libraries/technology/ip_agi027_xxxx/ram/README.txt

 README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ram
-VERSION 01 - 20231110
+VERSION 02 - 20231218
 
 Contents:
 
@@ -11,7 +11,8 @@ Contents:
 6) Implementation options (LUTs or block RAM)
 7) Synthesis trials
 8) Agilex7 issues
-9) References
+9) Remarks
+10) References
 
 
 
@@ -32,6 +33,7 @@ Contents:
                                  Not available, because the Agilex 7 does not support ratio widths in combination with true dual port mode.
 
 
+
 2) ROM components:
    ip_agi027_xxxx_rom_r_w      = Not available and not needed, because the ip_agi027_xxxx_ram_r_w can be used for ROM IP by not connecting the
                                  write port. The IP could be created and than the vhd file can be derived from the generated HDL files and the
@@ -44,7 +46,7 @@ Contents:
   The RAM IPs were ported manually from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxx by creating it in Quartus
   using the same parameter settings by:
 
-   - methode A:
+   - method A:
     . copy original ip_arria_e2sg_<ram_name>.vhd and ip_arria_e2sg_<ram_name>.ip files.
     . rename ip_arria_e2sg_<ram_name>.ip and .vhd into ip_agi027_xxxx_<ram_name>.ip and .vhd (also replace name inside the .vhd file)
     . open in to Quartus 23.2.0 build 94, set device family to Agilex7 and device part to AGIB027R31A1I1VB. 
@@ -55,7 +57,7 @@ Contents:
       necessary to make it work.
     . git commit also the ip_agi027_xxxx_<ram_name>.ip to preserve the original in case it needs to be modified.
 
-   - methode B:
+   - method B:
     . copy original ip_arria_e2sg_<ram_name>.vhd file.
     . rename ip_arria_e2sg_<ram_name>.vhd into ip_agi027_xxxx_<ram_name>.vhd (also replace name inside the .vhd file).
     . open ip_arria_e2sg_<ram_name>.ip file in Quartus 19.4.0 build 64. No device family and device part need to be set.
@@ -235,7 +237,23 @@ Contents:
       as there is also no testbench for the underlying 'common_ram_crw_crw_ratio' file that was utilized.
 
 
-9) References:
+
+9)    Remarks:
+
+  a)  For tech_memory_ram_crw_crw the ip_agi027_xxxx_rw_rw is added, because in a lot of files at the higher layer common_ram_crw_crw.vhd is used.
+      It is not preferable to add an extra generic or the technology there, to generate the right used component.
+      So it is better to implement a clock domain cross component such as dp_fifo_dc_arr or common_reg_cross_domain (to save logic and/or RAM)
+      when needed at a design at the higher layer. A lot of designs cannot have an extra latency, and then one clock domain is also an option.
+  b)  For tech_memory_ram_crwk_crw the ip_agi027_xxxx_rw_rw is added, because the ip_agi027_xxxx_crk_cw has one read and one write port and 
+      the mm port should have read/write possibility to check if standard rewrite to '0'-values is going well by writing other values then '0'
+      before to mm domain. To keep this therefore a DC_FIFO in combination with a MUX need to be added. (Also it is possible to check this with mm reg.)
+      And because only one clock domain is used in the other designs by the Agilex 7, ram_rw_rw makes the most suitable solution. 
+      To have the ratio option is less important. That one can also be added with dp_repack if needed.
+      This results in: one clock domain and a fixed datarate.
+
+
+
+10) References:
 
   [1] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/true-dual-port-dual-clock-emulator.html
   [2] https://www.intel.com/content/www/us/en/docs/programmable/683241/23-2/embedded-memory-configurations.html

libraries/technology/memory/tech_memory_ram_crwk_crw.vhd

@@ -23,9 +23,12 @@
 -- Remark:
 --   The Agilex 7 (agi027_xxxx) doesn't support this IP as used for previous
 --   FPGA technology identifiers (device types), and unfortunately, the rwk_rw
---   IP variant isn't supported either. Instead, the crk_cw IP can be created
+--   IP variant isn't supported either. Instead, the crk_cw IP can be used
 --   when necessary. For more details please refer the README.txt in the
 --   ip_agi027_xxxx/ram/ folder.
+-- . For Agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added
+--   to this package, but it is only supporting clock_b and a ratio of 1.
+--   (So it can be used in the diag_databuffer).
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -39,6 +42,7 @@ library ip_arria10_ram_lib;
 library ip_arria10_e3sge3_ram_lib;
 library ip_arria10_e1sg_ram_lib;
 library ip_arria10_e2sg_ram_lib;
+library ip_agi027_xxxx_ram_lib;
 
 entity tech_memory_ram_crwk_crw is  -- support different port data widths and corresponding address ranges
   generic (
@@ -103,4 +107,10 @@ begin
     port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_ram_rw_rw
+    generic map (false, g_adr_b_w, g_dat_b_w, g_nof_words_b, g_rd_latency, g_init_file)
+    port map (address_a, address_b, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+  end generate;
+
 end architecture;