clock generation re-done due to delta-cycle issue

boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd

@@ -52,7 +52,7 @@ ENTITY ctrl_unb1_board IS
     g_stamp_svn       : NATURAL := 0;
     g_design_note     : STRING  := "UNUSED";
     g_mm_clk_freq     : NATURAL := c_unb1_board_mm_clk_freq_125M;  -- default use same MM clock as for TSE clock
-    g_mm_clk_use_pll  : BOOLEAN := FALSE;
+    g_xo_clk_use_pll  : BOOLEAN := FALSE;
     
     ----------------------------------------------------------------------------
     -- External CLK
@@ -141,9 +141,11 @@ ENTITY ctrl_unb1_board IS
     mm_clk_out             : OUT STD_LOGIC;
 
     mm_locked              : IN  STD_LOGIC := '0'; -- from QSYS
+    mm_locked_out          : OUT STD_LOGIC;
     mm_rst                 : OUT STD_LOGIC;
 
     epcs_clk               : IN  STD_LOGIC := '0'; -- from QSYS
+    epcs_clk_out           : OUT STD_LOGIC;
 
     
     dp_rst                 : OUT STD_LOGIC;
@@ -151,7 +153,7 @@ ENTITY ctrl_unb1_board IS
     dp_phs_clk_vec         : OUT STD_LOGIC_VECTOR(g_dp_phs_clk_vec_w-1 DOWNTO 0);   -- divided and phase shifted from 200 MHz CLK system clock when a PLL is used
     dp_pps                 : OUT STD_LOGIC;   -- PPS in dp_clk domain
     dp_rst_in              : IN  STD_LOGIC;   -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
-    dp_clk_in              : IN  STD_LOGIC;   -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk (due to dp_clk <= i_dp_clk assignment)
+    dp_clk_in              : IN  STD_LOGIC;   -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
 
     cal_rec_clk            : OUT STD_LOGIC;
 
@@ -205,6 +207,7 @@ ENTITY ctrl_unb1_board IS
     reg_ppsh_miso          : OUT t_mem_miso;
     
     -- eth1g control&monitoring
+    eth1g_tse_clk_out      : OUT STD_LOGIC;
     eth1g_tse_clk          : IN  STD_LOGIC := '0';
     eth1g_mm_rst           : IN  STD_LOGIC;
     eth1g_tse_mosi         : IN  t_mem_mosi;  -- ETH TSE MAC registers
@@ -269,15 +272,11 @@ ARCHITECTURE str OF ctrl_unb1_board IS
   SIGNAL i_xo_rst               : STD_LOGIC;
   SIGNAL i_xo_rst_n             : STD_LOGIC;
   SIGNAL i_mm_rst               : STD_LOGIC;
-  SIGNAL i_mm_clk               : STD_LOGIC;
-  SIGNAL i_mm_locked            : STD_LOGIC;
-  SIGNAL i_epcs_clk             : STD_LOGIC := '1';
-  SIGNAL i_cal_rec_clk          : STD_LOGIC := '1';
-  SIGNAL i_clk125               : STD_LOGIC := '1';
-  SIGNAL i_clk40                : STD_LOGIC := '1';
-  SIGNAL i_clk50                : STD_LOGIC := '1';
-  SIGNAL i_clk25                : STD_LOGIC := '1';
-  SIGNAL i_dp_clk               : STD_LOGIC := '1';
+
+  SIGNAL clk125M                : STD_LOGIC := '1';
+  SIGNAL clk40M                 : STD_LOGIC := '1';
+  SIGNAL clk50M                 : STD_LOGIC := '1';
+  SIGNAL clk20M                 : STD_LOGIC := '1';
 
   SIGNAL mm_wdi                 : STD_LOGIC;
   SIGNAL eth1g_st_clk           : STD_LOGIC;
@@ -318,10 +317,11 @@ BEGIN
   xo_clk     <= i_xo_clk;
   xo_rst     <= i_xo_rst;
   xo_rst_n   <= i_xo_rst_n;
-  mm_clk_out <= i_mm_clk;
   mm_rst     <= i_mm_rst;
 
-  cal_rec_clk <= i_cal_rec_clk;
+  epcs_clk_out      <= clk20M;
+  cal_rec_clk       <= clk40M;
+  eth1g_tse_clk_out <= clk125M;
 
   
   -----------------------------------------------------------------------------
@@ -381,15 +381,10 @@ BEGIN
 
 
 
-
-  gen_clk25_pll: IF g_mm_clk_use_pll = TRUE GENERATE
-    gen_mm_clk_50: IF g_mm_clk_freq = c_unb1_board_mm_clk_freq_50M GENERATE
-      i_mm_clk <= i_clk50;
-    END GENERATE;
-
-    gen_mm_clk_125: IF g_mm_clk_freq = c_unb1_board_mm_clk_freq_125M GENERATE
-      i_mm_clk <= i_clk125;
-    END GENERATE;
+  gen_clk25_pll: IF g_xo_clk_use_pll = TRUE GENERATE
+    mm_clk_out <= clk125M WHEN g_mm_clk_freq = c_unb1_board_mm_clk_freq_125M ELSE
+                  clk50M  WHEN g_mm_clk_freq = c_unb1_board_mm_clk_freq_50M  ELSE
+                  clk50M;
 
     u_unb1_board_clk25_pll : ENTITY work.unb1_board_clk25_pll
     GENERIC MAP (
@@ -398,23 +393,14 @@ BEGIN
     PORT MAP (
       arst       => i_xo_rst,
       clk25      => i_xo_clk,
-      c0_clk20   => i_epcs_clk,
-      c1_clk40   => i_cal_rec_clk,
-      c2_clk50   => i_clk50,
-      c3_clk125  => i_clk125,
-      pll_locked => i_mm_locked
+      c0_clk20   => clk20M,
+      c1_clk40   => clk40M,
+      c2_clk50   => clk50M,
+      c3_clk125  => clk125M,
+      pll_locked => mm_locked_out
     );
   END GENERATE;
 
-  no_clk25_pll: IF g_mm_clk_use_pll = FALSE GENERATE
-    i_mm_clk    <= mm_clk;
-    i_epcs_clk  <= epcs_clk;
-    i_clk125    <= eth1g_tse_clk;
-    i_mm_locked <= mm_locked;
-  END GENERATE;
-
-
-
 
 
   u_unb1_board_node_ctrl : ENTITY work.unb1_board_node_ctrl
@@ -424,8 +410,8 @@ BEGIN
   PORT MAP (
     xo_clk      => i_xo_clk,
     xo_rst_n    => i_xo_rst_n,
-    sys_clk     => i_mm_clk,
-    sys_locked  => i_mm_locked,
+    sys_clk     => mm_clk,
+    sys_locked  => mm_locked,
     sys_rst     => i_mm_rst,
     cal_clk     => '0',
     cal_rst     => OPEN,
@@ -453,7 +439,7 @@ BEGIN
     g_design_note => g_design_note
   )
   PORT MAP (
-    mm_clk      => i_mm_clk,
+    mm_clk      => mm_clk,
     mm_rst      => i_mm_rst,
 
     hw_version  => VERSION,
@@ -507,7 +493,7 @@ BEGIN
   u_toggle : ENTITY common_lib.common_toggle
   PORT MAP (
     rst         => i_mm_rst,
-    clk         => i_mm_clk,
+    clk         => mm_clk,
     in_dat      => mm_pulse_s,
     out_dat     => led_toggle
   );
@@ -524,7 +510,7 @@ BEGIN
   u_unb1_board_wdi_reg : ENTITY work.unb1_board_wdi_reg
   PORT MAP (
     mm_rst              => i_mm_rst,
-    mm_clk              => i_mm_clk,
+    mm_clk              => mm_clk,
      
     sla_in              => reg_wdi_mosi,
     sla_out             => reg_wdi_miso,
@@ -542,9 +528,9 @@ BEGIN
   u_mms_remu: ENTITY remu_lib.mms_remu
   PORT MAP (
     mm_rst             => i_mm_rst,
-    mm_clk             => i_mm_clk,
+    mm_clk             => mm_clk,
 
-    epcs_clk           => i_epcs_clk,
+    epcs_clk           => epcs_clk,
 
     remu_mosi          => reg_remu_mosi,
     remu_miso          => reg_remu_miso
@@ -559,9 +545,9 @@ BEGIN
   )
   PORT MAP (
     mm_rst             => i_mm_rst,
-    mm_clk             => i_mm_clk,
+    mm_clk             => mm_clk,
 
-    epcs_clk           => i_epcs_clk,
+    epcs_clk           => epcs_clk,
 
     epcs_mosi          => reg_epcs_mosi,
     epcs_miso          => reg_epcs_miso,
@@ -590,7 +576,7 @@ BEGIN
   PORT MAP (
     -- Clocks and reset
     mm_rst           => i_mm_rst,
-    mm_clk           => i_mm_clk,
+    mm_clk           => mm_clk,
     st_rst           => dp_rst_in,
     st_clk           => dp_clk_in,
     pps_ext          => ext_pps,           -- with unknown but constant phase to st_clk
@@ -619,7 +605,7 @@ BEGIN
   PORT MAP (
     -- Clocks and reset
     mm_rst    => i_mm_rst,
-    mm_clk    => i_mm_clk,
+    mm_clk    => mm_clk,
     mm_start  => mm_board_sens_start,
     
     -- Memory-mapped clock domain
@@ -664,7 +650,7 @@ BEGIN
     END GENERATE;
 
     gen_separate_clk: IF g_udp_offload=FALSE GENERATE
-      eth1g_st_clk <= i_mm_clk;
+      eth1g_st_clk <= mm_clk;
       eth1g_st_rst <= eth1g_mm_rst;
     END GENERATE;
 
@@ -675,9 +661,9 @@ BEGIN
     )
     PORT MAP (
       -- Clocks and reset
-      mm_rst            => eth1g_mm_rst,-- use reset from SOPC
-      mm_clk            => i_mm_clk,    -- use mm_clk direct
-      eth_clk           => i_clk125,    -- use the dedicated 125 MHz tse_clock, independent of the mm_clk 
+      mm_rst            => eth1g_mm_rst,  -- use reset from QSYS
+      mm_clk            => mm_clk,        -- use mm_clk direct
+      eth_clk           => eth1g_tse_clk, -- use the dedicated 125 MHz tse_clock, independent of the mm_clk 
       st_rst            => eth1g_st_rst,
       st_clk            => eth1g_st_clk,