Comment update. Little more margin in latency checks.

libraries/io/eth/tb/vhdl/tb_eth_tester.vhd

@@ -25,8 +25,9 @@
 --
 -- Usage:
 -- > as 8
--- # Cannot use run -a when g_loopback_eth=TRUE and g_eth_sim_level=0, because
--- # the TSE IP model remains active internally after tb_end
+-- # * E.g. view sosi/data signals in dut/gen_streams/u_rx and u_tx
+-- # * Cannot use run -a when g_loopback_eth=TRUE and g_eth_sim_level=0,
+-- #   because the TSE IP model remains active internally after tb_end
 -- > run 100 us  # when g_loopback_eth=TRUE and g_eth_sim_level=0, else:
 -- > run -a
 --
@@ -357,7 +358,7 @@ BEGIN
             "ETH bit rate total :" &
             " c_eth_nof_bps_total = " & REAL'IMAGE(c_eth_nof_bps_total) & " bps");
     END IF;
-    ASSERT c_eth_nof_bps_total < 10.0**9 REPORT "Tx flow control will keep ETH bitrate < 1Gbps." SEVERITY WARNING;
+    ASSERT c_eth_nof_bps_total < 10.0**9 REPORT "Tx flow control will keep ETH bitrate < 1Gbps." SEVERITY NOTE;
 
     -------------------------------------------------------------------------
     -- Verification: Total counts
@@ -513,15 +514,15 @@ BEGIN
           IF g_loopback_eth = TRUE THEN
             IF g_nof_streams = 1 THEN
               IF g_eth_sim_level = 0 THEN
-                ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_tech_tse, 1) REPORT
+                ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_tech_tse, 10) REPORT
                     c_tb_str & "Wrong rx latency using tech_tse interface" SEVERITY ERROR;
               ELSIF g_eth_sim_level = 1 THEN
-                ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_sim_tse, 1) REPORT
+                ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_sim_tse, 10) REPORT
                     c_tb_str & "Wrong rx latency using sim_tse interface" SEVERITY ERROR;
               END IF;
             END IF;
           ELSE
-            ASSERT rx_mon_latency_arr(I) = c_rx_exp_latency_st REPORT
+            ASSERT almost_equal(rx_mon_latency_arr(I), c_rx_exp_latency_st, 0) REPORT
                 c_tb_str & "Wrong rx latency using st interface (" & NATURAL'IMAGE(I) & ")" SEVERITY ERROR;
           END IF;
         END IF;
@@ -602,7 +603,7 @@ BEGIN
       tse_init <= '0';
     END GENERATE;
     use_tech_tse : IF g_eth_sim_level = 0 GENERATE
-      p_link : PROCESS(eth_txp)
+      p_eth_link : PROCESS(eth_txp)
       BEGIN
         eth_rxp <= TRANSPORT eth_txp AFTER 12 ns;  -- apply cable delay
         eth_corrupt <= '0';

libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd

@@ -28,6 +28,7 @@
 -- Usage:
 --   > as 8
 --   > run -all
+--   Takes about 25 m
 
 LIBRARY IEEE, diag_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -155,7 +156,6 @@ BEGIN
   -- . BG supports samples_per_packet >= 2, BG treats samples_per_packet = 1 as 2
   -- . ETH MAC pads samples_per_packet <= 6 to 6, to have minimum packet length of 64 octets,
   --   because hdr = 14 + 20 + 8 + 12 and crc = 4 have 58 octets.
-
   u_st_len2 : ENTITY work.tb_eth_tester GENERIC MAP (20, c_nof_sync, 1, FALSE, 1, FALSE,
                                                      ('1', '1', 2, c_nof_blk, c_gap_len, 0, c_high, 0),
                                                      c_bg_ctrl_rst)