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Commit 10bf4ff5 authored by Pepping's avatar Pepping
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-Added functionality that uses sync_in to capture the current bsn and the...

-Added functionality that uses sync_in to capture the current bsn and the number of cycles between the last sop and the pulse on sync_in. 
-Added input port sync_in
-Changed default value g_log_first_bsn to TRUE
-NOTE THAT g_log_first_bsn IS NOW ACTUALLY USED!!!!

parent d856d911
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...@@ -30,8 +30,12 @@ ...@@ -30,8 +30,12 @@
-- . mon_nof_sop = number of sop during last sync interval -- . mon_nof_sop = number of sop during last sync interval
-- . mon_nof_err = number of err at eop during last sync interval -- . mon_nof_err = number of err at eop during last sync interval
-- . mon_nof_valid = number of valid during last sync interval; -- . mon_nof_valid = number of valid during last sync interval;
-- . mon_bsn_first = BSN at the first SOP that came in -- . mon_bsn_first = BSN at the first SOP that came in (When g_log_first_bsn = TRUE)
-- . mon_bsn_first_cycle_cnt = number of cycles after rst at which mon_bsn_first was logged -- . mon_bsn_first_cycle_cnt = number of cycles after rst at which mon_bsn_first was logged (When g_log_first_bsn = TRUE)
--
-- . mon_bsn_first = BSN at the moment sync_in is pulsed (When g_log_first_bsn = FALSE)
-- . mon_bsn_first_cycle_cnt = number of cycles after the last sop befor sync_in is pulsed (When g_log_first_bsn = FALSE)
--
-- Remarks: -- Remarks:
-- . Assumes RL > 0 so each active valid indicates a new data (with RL = 0 the -- . Assumes RL > 0 so each active valid indicates a new data (with RL = 0 the
-- valid remains active until an acknowledge by ready) -- valid remains active until an acknowledge by ready)
...@@ -47,7 +51,7 @@ ENTITY dp_bsn_monitor IS ...@@ -47,7 +51,7 @@ ENTITY dp_bsn_monitor IS
GENERIC ( GENERIC (
g_sync_timeout : NATURAL := 200*10**6; -- choose >= nof clk cycles per sync period g_sync_timeout : NATURAL := 200*10**6; -- choose >= nof clk cycles per sync period
g_error_bi : NATURAL := 0; g_error_bi : NATURAL := 0;
g_log_first_bsn : BOOLEAN := FALSE -- Logs first BSN + cycle count. Useful when using BSN aligner. g_log_first_bsn : BOOLEAN := TRUE -- Logs first BSN + cycle count. Useful when using BSN aligner.
); );
PORT ( PORT (
rst : IN STD_LOGIC := '0'; rst : IN STD_LOGIC := '0';
...@@ -56,7 +60,7 @@ ENTITY dp_bsn_monitor IS ...@@ -56,7 +60,7 @@ ENTITY dp_bsn_monitor IS
-- ST interface -- ST interface
in_siso : IN t_dp_siso; in_siso : IN t_dp_siso;
in_sosi : IN t_dp_sosi; in_sosi : IN t_dp_sosi;
sync_in : IN STD_LOGIC := '0'; -- Sync input that samples the current bsn number and the number of clockcycles that have expired since the last sop
-- MM interface -- MM interface
-- . control -- . control
mon_evt : OUT STD_LOGIC; -- pulses when new monitor output is available regarding the previous sync interval mon_evt : OUT STD_LOGIC; -- pulses when new monitor output is available regarding the previous sync interval
...@@ -117,6 +121,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor IS ...@@ -117,6 +121,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor IS
SIGNAL i_mon_nof_valid : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0); SIGNAL i_mon_nof_valid : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0);
SIGNAL i_mon_bsn_first : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0); SIGNAL i_mon_bsn_first : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL i_mon_bsn_first_cycle_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); SIGNAL i_mon_bsn_first_cycle_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL i_current_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL cnt_cycle : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); SIGNAL cnt_cycle : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL sync_timeout_cnt : STD_LOGIC_VECTOR(c_sync_timeout_w-1 DOWNTO 0); SIGNAL sync_timeout_cnt : STD_LOGIC_VECTOR(c_sync_timeout_w-1 DOWNTO 0);
...@@ -134,6 +139,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor IS ...@@ -134,6 +139,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor IS
SIGNAL nxt_mon_nof_valid : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0); SIGNAL nxt_mon_nof_valid : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0);
SIGNAL nxt_mon_bsn_first : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0); SIGNAL nxt_mon_bsn_first : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
SIGNAL nxt_mon_bsn_first_cycle_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); SIGNAL nxt_mon_bsn_first_cycle_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL nxt_current_bsn : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
BEGIN BEGIN
...@@ -200,7 +206,6 @@ BEGIN ...@@ -200,7 +206,6 @@ BEGIN
err <= '0'; err <= '0';
sync <= '0'; sync <= '0';
bsn <= (OTHERS=>'0'); bsn <= (OTHERS=>'0');
first_sop <= '0';
-- output -- output
mon_evt <= '0'; mon_evt <= '0';
sync_timeout <= '0'; sync_timeout <= '0';
...@@ -212,6 +217,7 @@ BEGIN ...@@ -212,6 +217,7 @@ BEGIN
i_mon_nof_valid <= (OTHERS=>'0'); i_mon_nof_valid <= (OTHERS=>'0');
i_mon_bsn_first <= (OTHERS=>'0'); i_mon_bsn_first <= (OTHERS=>'0');
i_mon_bsn_first_cycle_cnt <= (OTHERS=>'0'); i_mon_bsn_first_cycle_cnt <= (OTHERS=>'0');
i_current_bsn <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN ELSIF rising_edge(clk) THEN
-- internal -- internal
ready <= nxt_ready; ready <= nxt_ready;
...@@ -233,10 +239,10 @@ BEGIN ...@@ -233,10 +239,10 @@ BEGIN
i_mon_nof_valid <= nxt_mon_nof_valid; i_mon_nof_valid <= nxt_mon_nof_valid;
i_mon_bsn_first <= nxt_mon_bsn_first; i_mon_bsn_first <= nxt_mon_bsn_first;
i_mon_bsn_first_cycle_cnt <= nxt_mon_bsn_first_cycle_cnt; i_mon_bsn_first_cycle_cnt <= nxt_mon_bsn_first_cycle_cnt;
i_current_bsn <= nxt_current_bsn;
END IF; END IF;
END PROCESS; END PROCESS;
-- siso -- siso
nxt_ready <= in_siso.ready; nxt_ready <= in_siso.ready;
nxt_xon <= in_siso.xon; nxt_xon <= in_siso.xon;
...@@ -261,6 +267,8 @@ BEGIN ...@@ -261,6 +267,8 @@ BEGIN
r_stable_ack => sync r_stable_ack => sync
); );
-- Sample the BSN, because BSN is only valid during sop.
nxt_current_bsn <= in_sosi.bsn(c_bsn_w-1 DOWNTO 0) WHEN in_sosi.sop='1' ELSE i_current_bsn;
-- sosi -- sosi
-- . no need to AND sop, eop with valid, because can only be active when valid = '1' -- . no need to AND sop, eop with valid, because can only be active when valid = '1'
...@@ -271,10 +279,18 @@ BEGIN ...@@ -271,10 +279,18 @@ BEGIN
nxt_err <= in_sosi.err(g_error_bi) WHEN in_sosi.eop='1' ELSE '0'; -- assume sosi.err(g_error_bi) = '1' at eop indicates an error nxt_err <= in_sosi.err(g_error_bi) WHEN in_sosi.eop='1' ELSE '0'; -- assume sosi.err(g_error_bi) = '1' at eop indicates an error
nxt_bsn <= in_sosi.bsn(c_bsn_w-1 DOWNTO 0) WHEN in_sosi.sop='1' ELSE bsn; -- keep bsn as defined at sop nxt_bsn <= in_sosi.bsn(c_bsn_w-1 DOWNTO 0) WHEN in_sosi.sop='1' ELSE bsn; -- keep bsn as defined at sop
gen_log_first_bsn : IF g_log_first_bsn = TRUE GENERATE
nxt_mon_bsn_first <= in_sosi.bsn(c_bsn_w-1 DOWNTO 0) WHEN first_sop='0' AND in_sosi.sop='1' ELSE i_mon_bsn_first; nxt_mon_bsn_first <= in_sosi.bsn(c_bsn_w-1 DOWNTO 0) WHEN first_sop='0' AND in_sosi.sop='1' ELSE i_mon_bsn_first;
nxt_mon_bsn_first_cycle_cnt <= cnt_cycle WHEN first_sop='0' AND in_sosi.sop='1' ELSE i_mon_bsn_first_cycle_cnt; nxt_mon_bsn_first_cycle_cnt <= cnt_cycle WHEN first_sop='0' AND in_sosi.sop='1' ELSE i_mon_bsn_first_cycle_cnt;
END GENERATE;
nxt_first_sop <= '1' WHEN first_sop='0' AND in_sosi.sop='1' ELSE first_sop; nxt_first_sop <= '1' WHEN first_sop='0' AND in_sosi.sop='1' ELSE first_sop;
gen_sync_in_enable : IF g_log_first_bsn = FALSE GENERATE
nxt_mon_bsn_first <= i_current_bsn WHEN sync_in = '1' ELSE i_mon_bsn_first;
nxt_mon_bsn_first_cycle_cnt <= cnt_cycle WHEN sync_in = '1' ELSE i_mon_bsn_first_cycle_cnt;
END GENERATE;
u_cnt_sop : ENTITY common_lib.common_counter u_cnt_sop : ENTITY common_lib.common_counter
GENERIC MAP ( GENERIC MAP (
g_width => c_cnt_sop_w g_width => c_cnt_sop_w
...@@ -318,10 +334,12 @@ BEGIN ...@@ -318,10 +334,12 @@ BEGIN
PORT MAP ( PORT MAP (
rst => rst, rst => rst,
clk => clk, clk => clk,
cnt_clr => '0', cnt_clr => in_sosi.sop,
cnt_en => '1', cnt_en => '1',
count => cnt_cycle count => cnt_cycle
); );
END rtl; END rtl;
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