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Commit 0e1106fa authored by Eric Kooistra's avatar Eric Kooistra
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Add bs_new_sync_interval.

parent 142d16c3
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1 merge request!283Resolve L2SDP-696
...@@ -76,7 +76,8 @@ ENTITY dp_bsn_source_v2 IS ...@@ -76,7 +76,8 @@ ENTITY dp_bsn_source_v2 IS
dp_on_pps : IN STD_LOGIC; dp_on_pps : IN STD_LOGIC;
dp_on_status : OUT STD_LOGIC; -- = src_out.valid dp_on_status : OUT STD_LOGIC; -- = src_out.valid
bs_restart : OUT STD_LOGIC; -- = src_out.sop for first sop after dp_on went high bs_restart : OUT STD_LOGIC; -- = src_out.sync for first sync after dp_on went high
bs_new_interval : OUT STD_LOGIC; -- = active during first src_out.sync interval
nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w); nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0'); bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
...@@ -107,7 +108,10 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS ...@@ -107,7 +108,10 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_src_out : t_dp_sosi := c_dp_sosi_init; SIGNAL i_src_out : t_dp_sosi := c_dp_sosi_init;
SIGNAL nxt_src_out : t_dp_sosi; SIGNAL nxt_src_out : t_dp_sosi;
SIGNAL nxt_bs_restart : STD_LOGIC; SIGNAL i_bs_restart : STD_LOGIC;
SIGNAL nxt_bs_restart : STD_LOGIC;
SIGNAL i_bs_new_interval : STD_LOGIC;
SIGNAL reg_bs_new_interval : STD_LOGIC;
SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0); SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0); SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
...@@ -121,6 +125,8 @@ BEGIN ...@@ -121,6 +125,8 @@ BEGIN
src_out <= i_src_out; src_out <= i_src_out;
dp_on_status <= i_src_out.valid; dp_on_status <= i_src_out.valid;
bs_restart <= i_bs_restart;
bs_new_interval <= i_bs_new_interval;
p_state : PROCESS(sync, sync_size_cnt, nof_clk_per_sync, p_state : PROCESS(sync, sync_size_cnt, nof_clk_per_sync,
state, i_src_out, block_size_cnt, bsn_time_offset_cnt, state, i_src_out, block_size_cnt, bsn_time_offset_cnt,
...@@ -232,6 +238,10 @@ BEGIN ...@@ -232,6 +238,10 @@ BEGIN
-- to have bs_restart at first src_out.sync and src_out.sop. -- to have bs_restart at first src_out.sync and src_out.sop.
nxt_bs_restart <= nxt_src_out.valid AND NOT i_src_out.valid; nxt_bs_restart <= nxt_src_out.valid AND NOT i_src_out.valid;
i_bs_new_interval <= '1' WHEN i_bs_restart = '1' ELSE
'0' WHEN i_src_out.sync = '1' ELSE
reg_bs_new_interval;
p_clk : PROCESS(rst, clk) p_clk : PROCESS(rst, clk)
BEGIN BEGIN
IF rst='1' THEN IF rst='1' THEN
...@@ -241,7 +251,8 @@ BEGIN ...@@ -241,7 +251,8 @@ BEGIN
sync_size_cnt <= (OTHERS=>'0'); sync_size_cnt <= (OTHERS=>'0');
sync <= '0'; sync <= '0';
block_size_cnt <= (OTHERS=>'0'); block_size_cnt <= (OTHERS=>'0');
bs_restart <= '0'; i_bs_restart <= '0';
reg_bs_new_interval <= '0';
bsn_time_offset_cnt <= (OTHERS=>'0'); bsn_time_offset_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN ELSIF rising_edge(clk) THEN
prev_state <= state; prev_state <= state;
...@@ -250,7 +261,8 @@ BEGIN ...@@ -250,7 +261,8 @@ BEGIN
sync_size_cnt <= nxt_sync_size_cnt; sync_size_cnt <= nxt_sync_size_cnt;
sync <= nxt_sync; sync <= nxt_sync;
block_size_cnt <= nxt_block_size_cnt; block_size_cnt <= nxt_block_size_cnt;
bs_restart <= nxt_bs_restart; i_bs_restart <= nxt_bs_restart;
reg_bs_new_interval <= i_bs_new_interval;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt; bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
END IF; END IF;
END PROCESS; END PROCESS;
......
...@@ -52,7 +52,8 @@ ENTITY mms_dp_bsn_source_v2 IS ...@@ -52,7 +52,8 @@ ENTITY mms_dp_bsn_source_v2 IS
-- Streaming clock domain -- Streaming clock domain
bs_sosi : OUT t_dp_sosi; bs_sosi : OUT t_dp_sosi;
bs_restart : OUT STD_LOGIC -- pulse to indicate if the bsn_source has restarted bs_restart : OUT STD_LOGIC; -- pulse to indicate if the bsn_source has restarted
bs_new_interval : OUT STD_LOGIC -- level to indicate first sync interval if the bsn_source has restarted
); );
END mms_dp_bsn_source_v2; END mms_dp_bsn_source_v2;
...@@ -116,6 +117,7 @@ BEGIN ...@@ -116,6 +117,7 @@ BEGIN
dp_on_pps => dp_on_pps, dp_on_pps => dp_on_pps,
dp_on_status => dp_on_status, dp_on_status => dp_on_status,
bs_restart => bs_restart, bs_restart => bs_restart,
bs_new_interval => bs_new_interval,
bsn_init => bsn_init, bsn_init => bsn_init,
nof_clk_per_sync => nof_clk_per_sync, nof_clk_per_sync => nof_clk_per_sync,
bsn_time_offset => bsn_time_offset, bsn_time_offset => bsn_time_offset,
......
...@@ -124,6 +124,8 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS ...@@ -124,6 +124,8 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
SIGNAL dp_on_pps : STD_LOGIC := '0'; SIGNAL dp_on_pps : STD_LOGIC := '0';
SIGNAL dp_on_status : STD_LOGIC; SIGNAL dp_on_status : STD_LOGIC;
SIGNAL bs_restart : STD_LOGIC; SIGNAL bs_restart : STD_LOGIC;
SIGNAL bs_new_interval : STD_LOGIC;
SIGNAL tb_new_interval : STD_LOGIC := '0';
SIGNAL bsn_init : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL bsn_init : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL bs_sosi : t_dp_sosi; SIGNAL bs_sosi : t_dp_sosi;
...@@ -304,6 +306,23 @@ BEGIN ...@@ -304,6 +306,23 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
p_verify_bs_new_interval : PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF bs_restart = '1' THEN
ASSERT bs_new_interval = '1' REPORT "Wrong begin of bs_new_interval" SEVERITY ERROR;
tb_new_interval <= '1';
ELSIF bs_sosi.sync = '1' THEN
ASSERT bs_new_interval = '0' REPORT "Wrong end of bs_new_interval" SEVERITY ERROR;
tb_new_interval <= '0';
ELSIF tb_new_interval = '1' THEN
ASSERT bs_new_interval = '1' REPORT "Wrong level during bs_new_interval" SEVERITY ERROR;
ELSE
ASSERT bs_new_interval = '0' REPORT "Unexpected bs_new_interval" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- DUT: dp_bsn_source_v2 -- DUT: dp_bsn_source_v2
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -324,7 +343,8 @@ BEGIN ...@@ -324,7 +343,8 @@ BEGIN
dp_on_pps => dp_on_pps, dp_on_pps => dp_on_pps,
dp_on_status => dp_on_status, -- = src_out.valid dp_on_status => dp_on_status, -- = src_out.valid
bs_restart => bs_restart, -- = src_out.sop for first sop after dp_on went high bs_restart => bs_restart, -- = src_out.sync for first sync after dp_on went high
bs_new_interval => bs_new_interval, -- active during first src_out.sync interval
bsn_init => bsn_init, bsn_init => bsn_init,
bsn_time_offset => bsn_time_offset, bsn_time_offset => bsn_time_offset,
......
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