Added hdllib file for digital baseband converter

libraries/dig_receiver/dbbc/hdllib.cfg

+hdl_lib_name = dbbc
+hdl_library_clause_name = dbbc_lib
+hdl_lib_uses_synth = common mm dp common_OA
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dBBC_pkg.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/fir_40.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/coef_rom.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/fir_ram.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/fir_lifo.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/addr_gen.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/FIR_core.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/complex_fir/complex_fir.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dbbc_dds.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dbbc_mixer.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dBBC_interface.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/dBBC.vhd
+    
+test_bench_files = 
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/dbbc/src/vhdl/tb_test_generator.vhd

libraries/dig_receiver/test_generator/hdllib.cfg

@@ -14,8 +14,11 @@ synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/WNG.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/samp_add.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/dds_n.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_axi4_if.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_axi4.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_if.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/test_generator_mm.vhd
     
 test_bench_files = 
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/test_generator/src/vhdl/tb_test_generator.vhd