L2SDP-200, added test to tb_dp_block_from_mm.vhd

libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd

@@ -59,10 +59,10 @@ END tb_dp_block_from_mm;
 ARCHITECTURE tb OF tb_dp_block_from_mm IS
 
   CONSTANT c_nof_blocks    : NATURAL := g_step_size / g_data_size;
-  CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks;
+  CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks + g_data_size;  -- Size is 1 address more than needed, to check for oversized blocks.
   CONSTANT c_ram_adr_w     : NATURAL := ceil_log2(c_ram_data_size);
 
-  CONSTANT c_ram : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
+  CONSTANT c_ram           : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
 
   SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL clk               : STD_LOGIC := '1';
@@ -83,16 +83,22 @@ ARCHITECTURE tb OF tb_dp_block_from_mm IS
   SIGNAL wr_miso           : t_mem_miso;
 
   -- needed for init and verify
-  SIGNAL ram_wr_en  : STD_LOGIC := '0';
-  SIGNAL ram_wr_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
-  SIGNAL ram_wr_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
-  SIGNAL ram_rd_en  : STD_LOGIC := '0';
-  SIGNAL ram_rd_adr : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
-  SIGNAL ram_rd_dat : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
-  SIGNAL ram_rd_val : STD_LOGIC;
-
-  SIGNAL init_done     : STD_LOGIC := '0';
-  SIGNAL transfer_done : STD_LOGIC := '0';
+  SIGNAL ram_wr_en         : STD_LOGIC := '0';
+  SIGNAL ram_wr_adr        : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL ram_wr_dat        : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL ram_rd_en         : STD_LOGIC := '0';
+  SIGNAL ram_rd_adr        : STD_LOGIC_VECTOR(c_ram.adr_w-1 DOWNTO 0);
+  SIGNAL ram_rd_dat        : STD_LOGIC_VECTOR(c_ram.dat_w-1 DOWNTO 0);
+  SIGNAL ram_rd_val        : STD_LOGIC;
+  SIGNAL ram_prev_rd_val   : STD_LOGIC;
+
+  SIGNAL rd_nxt_data       : NATURAL := 0;
+  SIGNAL rd_data           : NATURAL := 0;
+
+  SIGNAL stop_address      : NATURAL := 0;
+
+  SIGNAL init_done         : STD_LOGIC := '0';
+  SIGNAL transfer_done     : STD_LOGIC := '0';
   
 BEGIN
 
@@ -110,7 +116,7 @@ BEGIN
     ram_wr_en <= '0';
     proc_common_wait_until_low(clk, rst);
     proc_common_wait_some_cycles(clk, 10);
-    FOR i IN 0 TO c_ram_data_size-1 LOOP
+    FOR i IN 0 TO c_ram_data_size - 1 LOOP  -- Write 1 address more than needed.
       ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
       ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
       ram_wr_en  <= '1'; 
@@ -128,25 +134,40 @@ BEGIN
     start_address <= 0;
     proc_common_wait_until_high(clk, init_done);
     FOR i IN 0 TO c_nof_blocks-1 LOOP
-      start_address <= i * g_data_size; 
+      start_address <= i * g_data_size;
+        
       start_pulse <= '1';
       proc_common_wait_some_cycles(clk, 1);
-      
       start_pulse <= '0';
+      
+      --stop_address  <= start_address + g_nof_data * g_step_size - g_data_size - 1;
+      stop_address  <= start_address + (g_nof_data - 1) * g_step_size + g_data_size - 1;
       proc_common_wait_until_high(clk, block_done);
     END LOOP;
-    proc_common_wait_some_cycles(clk, 1);  -- needed for dp_block_to_mm to proccess last word.
+    proc_common_wait_some_cycles(clk, 1);  -- Needed for dp_block_to_mm to proccess last word.
     transfer_done <= '1';
     WAIT;
   END PROCESS;
 
-  p_verify_read : PROCESS
+  p_verify_transfer : PROCESS
+  BEGIN
+    proc_common_wait_until_high(clk, init_done);
+    WHILE tb_end = '0' LOOP
+      WAIT UNTIL rising_edge(clk);
+      IF block_done = '1' THEN
+        ASSERT stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0)) REPORT "wrong data at mm_done signal, must be same as stop_address" SEVERITY ERROR;
+      END IF;
+    END LOOP;  
+    WAIT;
+  END PROCESS;
+
+  p_read_ram : PROCESS
   BEGIN
     ram_rd_en  <= '0';
     ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
     proc_common_wait_until_high(clk, transfer_done);
     ram_rd_en  <= '1';
-    FOR i IN 0 TO c_ram_data_size-1 LOOP  
+    FOR i IN 0 TO c_ram_data_size - 1 LOOP  -- Ask for 1 address more than needed.
       ram_rd_adr <= TO_UVEC(i, c_ram.adr_w);
       proc_common_wait_some_cycles(clk, 1);
     END LOOP;
@@ -157,15 +178,25 @@ BEGIN
     WAIT;
   END PROCESS;
 
-  p_verify_check: PROCESS
-    VARIABLE v_cnt: NATURAL := 0; 
+  ram_prev_rd_val <= ram_rd_val WHEN rising_edge(clk);
+
+  p_verify_read_ram_data: PROCESS
   BEGIN
+    --stop_address <= g_nof_data * g_step_size - 1;
+    rd_nxt_data  <= 1;
     proc_common_wait_until_high(clk, transfer_done);
     WHILE tb_end = '0' LOOP
       WAIT UNTIL rising_edge(clk);
-      IF ram_rd_val = '1' THEN
-        ASSERT v_cnt = TO_UINT(ram_rd_dat) REPORT "RAM values not equal" SEVERITY ERROR;
-        v_cnt := v_cnt + 1;
+      rd_data <= TO_UINT(ram_rd_dat);
+      IF rd_data > 0 THEN
+        IF ram_rd_val = '1' THEN
+          ASSERT rd_data = rd_nxt_data REPORT "wrong order of RAM values" SEVERITY ERROR;
+          ASSERT rd_data <= stop_address REPORT "wrong RAM values, greater then block size" SEVERITY ERROR;
+          rd_nxt_data <= rd_nxt_data + 1;
+        END IF;
+        IF ram_rd_val = '0' AND ram_prev_rd_val = '1' THEN  -- If ram_rd_val goes from hi tot lo.
+          ASSERT rd_data = stop_address REPORT "wrong last RAM values, not same as block size" SEVERITY ERROR;
+        END IF;
       END IF;
     END LOOP;
     WAIT;