Fixed issues in testbench. This version works properly.

applications/unb1_reorder/tb/python/tc_unb1_reorder_seq.py

@@ -40,7 +40,6 @@ import pi_diag_data_buffer
 import pi_diag_rx_seq
 import pi_io_ddr
 import pi_ss_ss_wide
-import dsp_test
 import mem_init_file
 
 from tools import *
@@ -65,15 +64,14 @@ if __name__ == "__main__":
     io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
         
     # Create instances for the periperals
+    c_ena_pre_transpose = True
+
     c_nof_streams   = 1
-    c_wr_chunksize  = 256
-    c_rd_chunksize  = 32
-    c_rd_nof_chunks = 8
-    c_rd_interval   = 32
+    c_wr_chunksize  = 176
+    c_rd_chunksize  = 16
+    c_rd_nof_chunks = 11
+    c_rd_interval   = c_rd_chunksize
     c_gapsize       = 0
-    c_nof_blocks    = 32
-    c_in_dat_w      = 64
-    c_bg_ram_size   = c_wr_chunksize * c_nof_blocks
     
     bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_streams, ramSizePerChannel=2**14)
     db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
@@ -81,25 +79,23 @@ if __name__ == "__main__":
     rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, nof_inst=c_nof_streams)
     
     # Create object for DDR register map
-    ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
+    ddr_status = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
     
     # Create subandselect instance for pre-transpose.   
     ss = pi_ss_ss_wide.PiSsSsWide (tc, io, c_wr_chunksize*c_rd_chunksize, c_nof_streams) 
     
-    # Create dsp_test instance for helpful methods
-    dsp_test_bg = dsp_test.DspTest(inDatW=c_in_dat_w)
     
     ###############################################################################
     #
     # Create setting for the pre-transpose (subbandselect)
     #
     ###############################################################################
-#    ss_list = []
-#    for i in range(c_wr_chunksize):
-#        for j in range(c_rd_chunksize):
-#           ss_list.append(i + j*c_wr_chunksize)
-#           
-#    ss.write_selects(ss_list)
+    if c_ena_pre_transpose:
+        ss_list = []
+        for i in range(c_wr_chunksize):
+            for j in range(c_rd_chunksize):
+               ss_list.append(i + j*c_wr_chunksize)
+        ss.write_selects(ss_list)
     
     
     ################################################################################
@@ -108,71 +104,52 @@ if __name__ == "__main__":
     # Wait for power up (reset release)
     io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
     
+    # Wait for the DDR memory to become available    
+    do_until_eq(ddr_status.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
+
     # Control defaults
-    nof_mon = 2
-    start_address = 0
-    #nof_words = 134217720
-    nof_words = 100000
+    nof_mon = sel_a_b(tc.sim, 1, 2)
+    
+    # Initialization
+    step_0 =  1
+    step_1 =  c_wr_chunksize                       #   176
+    step_2 = -c_wr_chunksize*(c_rd_interval-1)+1   # -2639
+
+    rx_seq.write_step_3(StepSize=step_2, vLevel=5)
+    rx_seq.write_step_2(StepSize=step_2, vLevel=5)
+    rx_seq.write_step_1(StepSize=step_1, vLevel=5)
+    rx_seq.write_step_0(StepSize=step_0, vLevel=5)
     
+    bg.write_block_gen_settings(samplesPerPacket=c_wr_chunksize, blocksPerSync=16, gapSize=0, BSNInit=0)
+
+    # Block sequence start
+    rx_seq.write_enable_cntr(vLevel=5)
+    tx_seq.write_enable_cntr(vLevel=5)
+    bg.write_enable()
+
+    # Wait for rx data
+    do_until_gt(rx_seq.read_cnt, ms_retry=3000, val=0, s_timeout=3600)
+
     for rep in range(tc.repeat):
         tc.append_log(5, '')
         tc.append_log(3, '>>> Rep-%d' % rep)
-    
-        # Initialization
-        tx_seq.write_disable(vLevel=5)
-        rx_seq.write_disable(vLevel=5)
-        
-        # Wait for the DDR memory to become available    
-        do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)
         
-    #    # Flush Tx FIFO
-    #    ddr.write_flush_pulse(vLevel=5)
-    #    io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
-    #    
-    #    # Set DDR controller in write mode and start writing
-    #    ddr.write_set_address(data=start_address, vLevel=5)
-    #    ddr.write_access_size(data=nof_words, vLevel=5)
-    #    ddr.write_mode_write(vLevel=5)
-    #    ddr.write_begin_access(vLevel=5)
-
-        # Tx sequence start
-        #tx_seq.write_enable_cntr(vLevel=5)
-
-        # Set and enable Block Generator 
-        bg.write_block_gen_settings(samplesPerPacket=256, blocksPerSync=16, gapSize=0, BSNInit=0)
-        bg.write_enable()
-        
-        # Rx sequence start
-        rx_seq.write_enable_cntr(vLevel=5)
-
-        
-        # Set DDR3 controller in write mode
-        ddr.write_mode_write()
-
         # Tx sequence monitor
         for mon in range(nof_mon):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
             tx_seq.read_cnt(vLevel=5)
-        
-        # Wait until controller write access is done
-        #do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)        
-        
-        # Rx sequence start
-        #rx_seq.write_enable_cntr(vLevel=5)
-        
-    #    # Set DDR3 controller in read mode and start reading
-    #    ddr.write_mode_read(vLevel=5)
-    #    ddr.write_begin_access(vLevel=5)
-        
+
         # Rx sequence monitor
         for mon in range(nof_mon):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
             rx_seq.read_cnt(vLevel=5)
         
-        # Wait until controller read access is done
-        #do_until_eq(ddr.read_done, ms_retry=3000, val=1, s_timeout=3600)        
-        
+        io.wait_for_time(hw_time=1, sim_time=(10, 'us'))
+
         rx_seq.read_result(vLevel=5)
+
+        if tc.get_result() != "PASSED":
+            break
         
     
     # End