-Fixed register name.

libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd

@@ -94,7 +94,7 @@ BEGIN
     slv_out    => mm_fields_out
   );
 
-  rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill_32b") DOWNTO field_lo(c_field_arr, "rd_fill_32b"));
+  rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") DOWNTO field_lo(c_field_arr, "rd_fill"));
       
 END str;