Updated description for unb2b_arp_ping.

applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt

@@ -684,18 +684,8 @@ Other:
 
 BSP - PD
 1) arp, ping
-- extend eth1g module library
-- create unb2b_arp_ping design library
-  . no eth1g files in this dir
-  . check clk delata-cycle assignments in ctrl_unb2b_board
-  . use eth from eth lib (so not from eth1g, as long as it can remain the same)
-- unb2b_arp_ping + eth1g_master.vhd + tb_unb2b_arp_ping based on tb_eth.vhd
 - reply arp and ping in eth1g_master
-- toggle pout_wdi (used to be done by unb_osy)
 - pass on other traffic to external master
-- EK: fix g_sim = TRUE and g_sim_level = 1 in tb_eth.vhd (sim_tse.vhd)
-- EK: create common_mem_wait_request_adapter.vhd, necessary to access TSE port
-      via the MM bus.
 ==> working unb2b_arp_ping in simulation
 ==> working unb2b_arp_ping on HW
 
@@ -712,7 +702,7 @@ BSP - PD
 
 3) unb2b_minimal_gp
 - create unb2b_minimal_gp design library (so not a revision of unb2b_minimal)
-- integrate MM bus using common_mem_bus.vhd and common_mem_master_mux.vhd
+- integrate MM bus
 - manually connect all ctrl_unb2b_minimal slaves to the MM bus
 ==> working unb2b_minimal_gp in simulation (at least compile, load, run 1 us)
 ==> working unb2b_minimal_gp on HW
@@ -722,6 +712,67 @@ BSP - PD
   mmm_<design_name> MM bus
 
 
+
+2) D42 SDP OPC-UA server prototype
+
+l2SDP-43: L2 STAT DD Location of SC-SDP translator function
+         Update downselect of location of OPC-UA translator (combined task of
+         SDP and station Control)
+         - different types of M&C (volume, high rate, low rate, time critical)
+           . only the low rate M&C will go via OPC-UA, so BF weights and statistics via
+             a separate UDP path between LCU2 and SDP
+           . what abpout high volume write flash (readback)
+         - BF weights with timestamp to apply in future, or immediately if in
+           the past.
+         - Statistics read or stream at PPS or shorter intervals. Also stream
+           low rate BST, because streaming is for any time critical monitoring
+           not only for high rate time critical.
+l2SDP-32: L3 SDP DD Monitoring and Control
+         Finish downselect of Gemini Protocol and Uniboard COntrol Protocol
+         (mainly task within SDP)
+         - GP-UCP, QSYS-RTL, NiosII-RTL
+         - risk of delay due to:
+           . complexity of porting to VHDL (64b-32b, Axi-Avalon, IP data mover)
+           . low TRL of GP
+           . tight SDP planning
+         - unclear or too little benifit of GP compared to UCP
+         - not used for SDP or DESP future, if we have a SOC then direct
+           OPC-UA via TCP/IP
+           
+L2SDP-1: Create unb2b_arp_ping on UniBoard2, to show that the VHDL works
+         (part of learning VHDL).
+         - why are the IP files in git and why have they changed on the branch, 
+           this change may be only a change in date 
+         - Get unb2b_minimal working on HW when synthesizedfrom git branch, is
+           it still working when created on the master branch?
+         - Compare synthesis report of unb2b_arp_ping and unb2b_minimal
+         - check UniBoard_FP7/UniBoard/trunk/Firmware/doc/howto/
+           how_to_write_VHDL.txt e.g. coding style, latches and debugging tips
+         - make sure that eth1g_master makes the same TSE and ETH settings as
+           unb_osy.c
+         - tb_unb2b_arp_ping should always work before trying synthesis or
+           commit
+         
+
+4) Write the SDP design documents and ICDs (EK)
+
+D19 SDP requirements specification (for DDR, CDR)
+D20 SDP architectural design document (for DDR, CDR)
+
+Jira EK : L5 SDP DD ADC input and timing
+             - ADC align @ sysref in JESD IP or in seperate RTL or in input
+               buffer?
+             - The sysref of the FPGA always arrives and arrives before the
+               data of the ADC, so sysref of FPGA is the stable reference for
+               ADC align that also works when an ADC is off.
+             - sysref of FPGA is PPS with 200M samples per period and can
+               serve as interface towards OpenCL. Define a sample sequence
+               number (SSN) that counts samples and is initialized at PPS.
+             - timing of WG
+             - new BSN source with BSN offset
+          
+
+
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 * Q2 = Increment 2
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