Constrain link_clk to match 200 MHz frame_clk

applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station.sdc

@@ -97,8 +97,58 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
 #-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
 #-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
 
+# JESD
+
+# The link_clk has clk contstraint of 100 MHz, but this seems not sufficient to
+# guarantee proper cross clock domain data transfer between the link_clk and
+# the 200 MHz frame_clk. Therefore use set_clock_uncertainty to enforce
+# constraints on link_clk and frame_clk that are somewhat more than Fmax = 200
+# MHz. To get a reasonable Fmax use Fmax reported for designs where the JESD
+# did not show bit errors or sample shifts.
+#
+# For unb2c e.g. Fmax = 218 MHz for link_clk and Fmax = 244 MHz for frame_clk
+# were achieved, so similar as for unb2b. Thererfore choose to use same Fmax
+# values as for unb2b,
+#
+# In Timing Anayser -> Tasks Report Setup Summary -> Start -> Report timing for
+# link_clk yields timing diagram. Paste set_clock_uncertainty constraint in
+# cli -> Report: Regenerate, to update timing results.
+#
+# link_clk 100 MHz:
+#      _________           ____
+#     |         |         |
+#     ^         v         ^
+#  ___|         |_________|
+#     0         5        10 ns
+#             <-----------*  = 5.727 ns for both rise-rise and rise-fall
+#     <------> = 10 - 5.727 = 4.263 ns --> 234 MHz
+#
+# frame_clk 200 MHz:
+#      ____      ____
+#     |    |    |
+#     ^    v    ^
+#  ___|    |____|
+#     0   2.5   5 ns
+#             <-*  = 0.496 ns for both rise-rise and rise-fall
+#     <------> = 5 - 0.496 = 4.504 ns --> 222 MHz
+#
+# Idem use same set_clock_uncertainty for fall-fall and fall_rise. Although
+# maybe only the rise-rise constraint is already sufficient.
+
+# Increase clock uncertainty to force link_clk to have Fmax > 234MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -rise_to [get_clocks {*|iopll_0|link_clk}]  5.727
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|link_clk}] -fall_to [get_clocks {*|iopll_0|link_clk}]  5.727
+
+# Increase clock uncertainty to force frame_clk to have Fmax > 222MHz
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -rise_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -rise_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+set_clock_uncertainty -fall_from [get_clocks {*|iopll_0|frame_clk}] -fall_to [get_clocks {*|iopll_0|frame_clk}]  0.496
+
 # false paths added for the jesd interface as these clocks are independent.
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
-set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
-set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+#set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+#set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]