Define BG and DB MM register sizes in diag_pkg.vhd.

libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd

@@ -45,7 +45,7 @@ end diag_block_gen_reg;
 
 architecture rtl of diag_block_gen_reg is                                                                                        
   
-  constant c_adrs_width : positive := 3;
+  constant c_adrs_width : positive := c_diag_bg_reg_adr_w;
   signal   mm_bg_ctrl   : t_diag_block_gen := g_diag_block_gen_rst;
   signal   dp_bg_ctrl   : t_diag_block_gen := g_diag_block_gen_rst;
                                                                                                                         

libraries/base/diag/src/vhdl/diag_pkg.vhd

@@ -98,6 +98,9 @@ PACKAGE diag_pkg IS
   -----------------------------------------------------------------------------
   
   -- control register
+  CONSTANT c_diag_bg_reg_nof_dat : NATURAL := 8;
+  CONSTANT c_diag_bg_reg_adr_w   : NATURAL := ceil_log2(c_diag_bg_reg_nof_dat);
+  
   CONSTANT c_diag_bg_mode_w               : NATURAL :=  8;
   CONSTANT c_diag_bg_samples_per_packet_w : NATURAL := 16;   
   CONSTANT c_diag_bg_blocks_per_sync_w    : NATURAL := 24;   
@@ -143,6 +146,9 @@ PACKAGE diag_pkg IS
   -----------------------------------------------------------------------------
   -- Data buffer
   -----------------------------------------------------------------------------
+  CONSTANT c_diag_db_reg_nof_dat : NATURAL := 2;
+  CONSTANT c_diag_db_reg_adr_w   : NATURAL := ceil_log2(c_diag_db_reg_nof_dat);
+  
   CONSTANT c_diag_db_max_data_w  : NATURAL := 32;
   
   TYPE t_diag_data_type_enum IS (