Instantiate ip_arria10_mac_10g_top (see IP README.txt) and use 13 bit CSR...

Instantiate ip_arria10_mac_10g_top (see IP README.txt) and use 13 bit CSR address width (INSERT_CSR_ADAPTOR=1 in ip_arria10_mac_10g.qsys).

libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd

@@ -31,6 +31,7 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_stratixiv
   ------------------------------------------------------------------------------
   
+  -- Copied from entity $RADIOHDL/libraries/technology/ip_stratixiv/mac_10g/generated/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
   COMPONENT ip_stratixiv_mac_10g IS
 	PORT (
 		csr_clk_clk                     : in  std_logic                     := '0';             --                    csr_clk.clk
@@ -77,14 +78,15 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  COMPONENT ip_arria10_mac_10g IS
+  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/mac_10g/ip/generated/sim/ip_arria10_mac_10g.vhd
+  COMPONENT ip_arria10_mac_10g_top IS
 	PORT (
 		csr_read                        : in  std_logic                     := '0';             --                        csr.read
 		csr_write                       : in  std_logic                     := '0';             --                           .write
 		csr_writedata                   : in  std_logic_vector(31 downto 0) := (others => '0'); --                           .writedata
 		csr_readdata                    : out std_logic_vector(31 downto 0);                    --                           .readdata
 		csr_waitrequest                 : out std_logic;                                        --                           .waitrequest
-		csr_address                     : in  std_logic_vector(9 downto 0)  := (others => '0'); --                           .address
+		csr_address                     : in  std_logic_vector(12 downto 0) := (others => '0'); --                           .address
 		tx_312_5_clk                    : in  std_logic                     := '0';             --               tx_312_5_clk.clk
 		tx_156_25_clk                   : in  std_logic                     := '0';             --              tx_156_25_clk.clk
 		rx_312_5_clk                    : in  std_logic                     := '0';             --               rx_312_5_clk.clk