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Commit 0b67c77b authored by Eric Kooistra's avatar Eric Kooistra
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Removed hdl_lib_excludes and replaced it by hdl_lib_uses_ip and hdl_lib_include_ip.

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tools/hdltool_readme.txt
+ 48
− 34
View file @ 0b67c77b
......@@ -559,12 +559,42 @@ f) hdllib.cfg key descriptions
The name of the HDL library, e.g. common, dp, unb1_minimal.
- hdl_library_clause_name =
The name of the HDL library as it is used in the VHDL LIBRARY clause, e.g. common_lib, dp_lib, unb1_minimal_lib.
'The name of the HDL library as it is used in the VHDL LIBRARY clause, e.g. common_lib, dp_lib, unb1_minimal_lib.
- hdl_lib_uses_synth =
List of HDL library names that are used in this HDL library for the 'synth_files', only the libraries that appear in
VHDL LIBRARY clauses need to be mentioned, all lower level libraries are found automatically.
- hdl_lib_uses_ip =
The 'hdl_lib_uses_ip' typically defines IP libraries that have multiple variants even within a specific technology (as specified
by toolset key 'technology_names'). However typically only one tech variant of the IP is used in a design. The
'hdl_lib_include_ip' key therefore defines the library that must be included in the list of library dependencies that are derived
from 'hdl_lib_uses_ip'. Hence the 'hdl_lib_uses_ip' key defines the multiple choice IP libraries that are available in this
library and the 'hdl_lib_include_ip' select which one (or more) are used by a higher level component (design). For tech libraries
with only one IP library variant the IP libraries should be listed at the 'hdl_lib_uses_synth' key or at both the
'hdl_lib_uses_ip' and 'hdl_lib_include_ip' key. If a multiple choice IP library can be included always, then it may also be
specified at the 'hdl_lib_uses_synth'.
Typically present, but unused IP is no problem. However for synthesis the constraint files of unused IP can cause problems.
Therefore then use 'hdl_lib_include_ip' to only include this IP library from the IP variants in 'hdl_lib_uses_ip'. An
example is to only include ip_stratixiv_ddr3_uphy_4g_800_master in unb1_ddr3 / io_ddr / tech_ddr by setting hdl_lib_include_ip
= ip_stratixiv_ddr3_uphy_4g_800_master in the hdllib.cfg of unb1_ddr3. Another example is ip_stratixiv_tse_sgmii_lvds for
tech_tse which is included by the board specific library unb1_board to avoid that the other ip_stratixiv_tse_sgmii_gx variant
is also include when it is not actually used. This example also shows that a 'hdl_lib_include_ip' can also occur at some
intermediate hierarchical component level in a design. The advantage is that the include of ip_stratixiv_tse_sgmii_gx now
automatically applies to all designs that instantiate unb1_board.
The exclusion can only be done when the component is instantiated as a component and not as a entity. Therefore the
exclusion is done at the IP level, because the IP is instantiated as component. Hence the exclusion works because for a
component instance that is not used, only the component declaration (in the component package) needs to be known by the
tools. Hence the exclusion makes use of the same VHDL component mechanism as the technology independence.
The exclusion is only done for synthesis, so not for simulation. The reason is that for simulation it is oke to keep the
library included and also necessary to avoid a compile error when the library is mentioned in a LIBRARY clause. For
IP libraries this occurs in the tech_*.vhd to declare IP libraries to ensure default binding in simulation, e.g. like in
tech_ddr_stratixiv.vhd. This IP library clause is ignored by synthesis, so then the exclusion causes no errors.
The difference between this 'hdl_lib_uses_ip' key and the 'hdl_lib_technology' key is that the HDL libraries with
'hdl_lib_technology' key value that does not match the specified technologies are not build. Whereas HDL libraries that
are excluded via the combination of 'hdl_lib_include_ip' and 'hdl_lib_uses_ip' are still created in the build directory, but
they are not used for that HDL library so they are excluded dynamically.
- hdl_lib_uses_sim =
List of HDL library names that are used in this HDL library for the 'test_bench_files', only the libraries that appear in
VHDL LIBRARY clauses need to be mentioned, all lower level libraries are found automatically.
......@@ -576,25 +606,8 @@ f) hdllib.cfg key descriptions
that libraries that are only needed for the test bench simulations also get included in the list of libraries for
synthesis. Often the 'test_bench_files' do not depend on other libraries, so then the 'hdl_lib_uses_sim' remains empty.
- hdl_lib_excludes =
Defines the libraries that must be excluded from the list of library dependencies that are derived from hdl_lib_uses_synth
and hdl_lib_uses_sim. The hdl_lib_excludes key can be used to exclude an IP library that is supported by the tech variant
of the IP but not actually used in the design. Typically present but unused IP is no problem, but for synthesis the
constraint files for unused IP can cause problems. Therefore then use hdl_lib_excludes to exclude this IP library. An
example is to exclude ip_stratixiv_ddr3_uphy_4g_800_slave if via io_ddr / tech_ddr only the
ip_stratixiv_ddr3_uphy_4g_800_master is used because only one DDR memory is used. The exclusion cannot be done at the io_ddr
or tech_ddr level, because these are instantiated as entities. Therefore the exclusion is done at the IP level because the
IP is instantiated as component. Hence the exclusion works because for a component instance that is not used only the
component declaration (in the component package) needs to be known by the tools. Hence the exclusion makes use of the same
VHDL component mechanism as the technology independence.
The exclusion is only done for synthesis, so not for simulation. The reason is that for simulation it is oke to keep the
library included and also necessary to avoid compile error when the library is mentioned in a LIBRARY clause. For
IP libraries this occurs in the tech_*.vhd to declare IP libraries to ensure default binding in simulation, e.g. like in
tech_ddr_stratixiv.vhd. This IP library clause is ignored by synthesis, so then the exclusion causes no errors.
The difference between this 'hdl_lib_excludes' key and the 'hdl_lib_technology' key is that the HDL libraries with
'hdl_lib_technology' key value that does not match the specified technologies are not build. Whereas HDL libraries that
are excluded with 'hdl_lib_excludes' are still created in the build directory, but they are not used for that HDL library
so they are excluded dynamically.
- hdl_lib_include_ip =
See 'hdl_lib_uses_ip' description.
- hdl_lib_technology =
The IP technology that this library is using or targets, e.g. ip_stratixiv for UniBoard1, ip_arria10 for UniBoard2. For generic HDL libraries use ''.
......@@ -874,13 +887,13 @@ b) quartus_config.py command line arguments:
Instead of the --compile option it is also an option to define a separate quartus_compile.py script.
c) quartus_* keys and synth_top_level_entity
. The quartus_* keys are now source oriented. Instead it may be better to redefine thme as target oriented. Eg. a
. The quartus_* keys are now source oriented. Instead it may be better to redefine them as target oriented. Eg. a
quartus_create_qsf key that defines to create a qsf file using the information listed in the values.
Whether a key is source oriented or target oriented depends on whether its files are use for one or more targets.
In general if a file is used for more targets then source oriented is prefered to avoid having to list the file
name twice. If a file is used only for one target then target oriented is prefered to be more clear about the
In general if a file is used for more targets then source oriented is preferred to avoid having to list the file
name twice. If a file is used only for one target then target oriented is preferred to be more clear about the
purpose of the key.
. The synth_top_level_entity enfoitrces the creation of a qpf and qsf. This kind of hidden behavior is not so nice.
. The synth_top_level_entity enforces the creation of a qpf and qsf. This kind of hidden behavior is not so nice.
Instead it is more clear to have an explicit quartus_create_qpf and quartus_create_qsf key to define this.
f) Generate Quartus IP key
......@@ -963,9 +976,10 @@ i) multiple libRootDirs for finding hdllib.cfg files
p) Python peripherals
The Python peripherals are still in the $UNB/Software/python/peripherals directory. At some time we need to move
these also to RadioHDL. The peripherals could be located central again or local in a src/python directory. An
intermediate scheme is also possible whereby the periperal is kept local but copied to a central build/python
directory by means of a python_config.py script. The advantage of a central directory is that the periperals
these also to RadioHDL. The peripherals could be located central again or local in a src/python directory. A first
step can be to svn copy the $UNB/Software/python dir to $RADIOHDL/software/python to become independent of the
$UNB tree. An intermediate scheme is also possible whereby the periperal is kept local but copied to a central
build/python directory by means of a python_config.py script. The advantage of a central directory is that the periperals
are grouped so that only a single Python search path is needed. The disadvantage of having a fixed central
location in SVN is that peripherals that are application specific also need to be located there. Another option
may be to use a synbolic link from a central directory to each local Python peripheral.
......@@ -1043,27 +1057,27 @@ that are actually used on our board. If we make a new board with another FPGA, t
r) Improve toolset scheme
The toolset defines the combination of Modelsim version and Quartus version. Currently there are two toolsets 'unb1' and 'unb2'. This
The toolset defines the combination of Modelsim version and Quartus version. Currently there are two toolsets 'unb1', 'unb2' and 'unb2a'. This
toolset scheme needs to be improved because:
- for python they are defined by the hdltool_<toolset>.cfg, but for the run_* bash scripts they are defined in set_modelsim and set_quartus,
can they be defined in a common source (eg. base on hdltool_<toolset>.cfg set an environment variable and use that for bash). The bash
can they be defined in a common source (eg. base on hdltool_<toolset>.cfg set an environment variable and uses that for bash). The bash
script must then be ran from the same terminal as where the python config script was used to set the environment variable, because otherwise
the environment variable is not set or may not be correct.
- the toolsets are tight to a board name 'unb1' (is that oke?) or should we use more general toolset names, or do we need a symbolic toolset names at all?
- there is also a 'site' level in the bash scripts (is that still needed?)
s) Declare IP libraries to ensure default binding in simulation.
Currently the IP library is declared in the technology VHDL file e.g. like 'LIBRARY ip_arria10_ddr4_4g_1600_altera_emif_150;' in tech_ddr_arria10.vhd.
This IP library clause is ignored by synthesis. The IP library must be mapped for simulation, because otherwise Modelsim gives
an error when it compiles the VHDL. Therefore the IP library can then not be excluded with hdl_lib_excludes key.
an error when it compiles the VHDL. Therefore the IP library can then not be excluded for simulation with 'hdl_lib_include_ip' key.
Alternatively the LIBRARY clause could be omitted if the IP library is added to the -L libraries search list of each simulation configuration the
Modelsim project file. This can be achieved adding the IP library to the modelsim_search_libraries key in the hdltool_unb2.cfg. However the problem is
then that if the IP library is not mapped to a directory then Modelsim will issue an error when it tries to search it.
The unb2_test uses almost all IP libraries and then the revision uses hdl_lib_excludes to exclude the IP libraries that are not needed. It is not
necessary to exclude all IP libraries that are not used, but at least the ones that will cause errors if their qip/sdc file is sourced.
--> For now keep the hdl_lib_excludes but only use it for synthesis, for simulation the hdl_lib_excludes is ignored.
--> For now keep the 'hdl_lib_include_ip' but only use it for synthesis. For simulation the 'hdl_lib_include_ip' is ignored. Which is fine because
for simulation there is no need to exclude IP libraries.
......
tools/oneclick/base/hdl_config.py
+ 134
− 82
View file @ 0b67c77b
......@@ -101,7 +101,10 @@ class HdlConfig:
for d in self.removed_dicts:
self.libs.remove_dict_from_list(d)
# Keep list of HDL library names
# Keep list of removed HDL library names
self.removed_lib_names = self.libs.get_key_values('hdl_lib_name', self.removed_dicts)
# Keep list of used HDL library names
self.lib_names = self.libs.get_key_values('hdl_lib_name')
# Check that there are no duplicate library names (eg. due to copying a hdlib.cfg without modifying the hdl_lib_name value)
......@@ -116,74 +119,128 @@ class HdlConfig:
self.lib_names = self.libs.get_key_values('hdl_lib_name')
def get_used_libs(self, build_type, lib_dict, arg_exclude_libs=[]):
"""Get the list of used HDL libraries from the lib_dict and remove the excluded libs.
- 'hdl_lib_uses_synth' and 'hdl_lib_uses_sim' define the used libraries that are directly used in this library
- 'hdl_lib_excludes' defines the libraries that must be excluded for synthesis
def get_used_libs(self, build_type, lib_dict, arg_include_ip_libs=[]):
"""Get the list of used HDL libraries from the lib_dict. Which libraries are actually used depends on the build_type:
The build_type can be:
'' uses all libraries from 'hdl_lib_uses_synth', 'hdl_lib_uses_ip' and 'hdl_lib_uses_sim' in the lib_dict
'sim' uses all libraries from 'hdl_lib_uses_synth', 'hdl_lib_uses_ip' and 'hdl_lib_uses_sim' in the lib_dict
'synth' uses all libraries from 'hdl_lib_uses_synth' in the lib_dict and from 'hdl_lib_uses_ip' it only uses the IP
libraries that are mentioned in the local 'hdl_lib_include_ip' key or in the global arg_include_ip_libs
The 'hdl_lib_uses_*' keys all appear locally in the same hdllib.cfg file. The 'hdl_lib_include_ip' key appears at this level or at
a higher level (design) library hdllib.cfg file to select which of all available 'hdl_lib_uses_ip' IP libraries will actually be
used in the design. The 'hdl_lib_include_ip' cannot appear in a lower level hdllib.cfg, because a lower level HDL library cannot
depend on a higher level HDL library. Therefore the IP libraries that need to be included from 'hdl_lib_uses_ip' will be known in
include_ip_libs.
"""
# Get use_libs
use_libs = []
# Get local library dependencies
use_synth_libs = []
use_ip_libs = []
use_sim_libs = []
include_ip_libs = []
if 'hdl_lib_uses_synth' in lib_dict:
use_libs = lib_dict['hdl_lib_uses_synth'].split()
if build_type=='sim':
use_synth_libs = lib_dict['hdl_lib_uses_synth'].split()
if 'hdl_lib_uses_ip' in lib_dict:
use_ip_libs += lib_dict['hdl_lib_uses_ip'].split()
if 'hdl_lib_uses_sim' in lib_dict:
use_libs += lib_dict['hdl_lib_uses_sim'].split()
# For synthesis remove exclude_libs from use_libs
# use list() to take local copy, to avoid next that default empty list argument arg_exclude_libs=[] gets disturbed
exclude_libs = list(arg_exclude_libs)
use_sim_libs += lib_dict['hdl_lib_uses_sim'].split()
if 'hdl_lib_include_ip' in lib_dict:
include_ip_libs = lib_dict['hdl_lib_include_ip'].split()
# Check that the used libraries indeed all exist. Otherwise exit, so that it only needs to be checked here
for lib_name in use_synth_libs:
if (lib_name not in self.lib_names) and (lib_name not in self.removed_lib_names):
sys.exit('Error : Unknown HDL library name %s in some hdl_lib_uses_synth key' % lib_name)
for lib_name in use_sim_libs:
if (lib_name not in self.lib_names) and (lib_name not in self.removed_lib_names):
sys.exit('Error : Unknown HDL library name %s in some hdl_lib_uses_sim key' % lib_name)
for lib_name in use_ip_libs:
if (lib_name not in self.lib_names) and (lib_name not in self.removed_lib_names):
sys.exit('Error : Unknown HDL library name %s in some hdl_lib_uses_ip key' % lib_name)
for lib_name in include_ip_libs:
if (lib_name not in self.lib_names) and (lib_name not in self.removed_lib_names):
sys.exit('Error : Unknown HDL library name %s in some hdl_lib_include_ip key' % lib_name)
# Append include_ip_libs from this level to the global list of arg_include_ip_libs
include_ip_libs = list(arg_include_ip_libs) + include_ip_libs
# Get the actually use_libs for lib_dict
use_libs = use_synth_libs + use_ip_libs + use_sim_libs # default include all IP, so ignore include_ip_libs
if build_type=='sim':
use_libs = use_synth_libs + use_ip_libs + use_sim_libs # for simulation included all IP, so ignore include_ip_libs
if build_type=='synth':
if 'hdl_lib_excludes' in lib_dict:
exclude_libs += lib_dict['hdl_lib_excludes'].split()
for exclude_lib in exclude_libs:
if exclude_lib in use_libs:
use_libs.remove(exclude_lib)
return use_libs, exclude_libs
def derive_all_use_libs(self, build_type, lib_name, arg_exclude_libs=[]):
use_libs = use_synth_libs
# For synthesis only keep the local use_ip_libs if it is mentioned in the global include_ip_libs. Vice versa also only
# include the global include_ip_libs if they appear in a local use_ip_libs, to avoid that an IP library that is mentioned
# in the global include_ip_libs gets included while it is not instantiated anywhere in the design.
for ip_lib in use_ip_libs:
if ip_lib in include_ip_libs:
use_libs += [ip_lib]
# Remove any duplicate library names from the lists
use_libs = cm.unique(use_libs)
include_ip_libs = cm.unique(include_ip_libs)
# Remove libraries that are in the removed technologies (use list() to take copy)
for lib_name in list(use_libs):
if lib_name in self.removed_lib_names:
use_libs.remove(lib_name)
for lib_name in list(include_ip_libs):
if lib_name in self.removed_lib_names:
include_ip_libs.remove(lib_name)
return use_libs, include_ip_libs
def derive_all_use_libs(self, build_type, lib_name, arg_include_ip_libs=[]):
"""Derive a list of all HDL libraries that the specified HDL lib_name library depends on.
The build_type can be:
'sim' uses both the 'hdl_lib_uses_synth' and the 'hdl_lib_uses_sim' key in the lib_dict,
'synth' uses only the 'hdl_lib_uses_synth' key in the lib_dict
The hdl_lib_uses_* key only needs to contain all libraries that are declared at the VHDL LIBRARY clauses of the
source files in this VHDL library. This derive_all_use_libs() will recursively find all deeper level VHDL libraries as well.
The arg_include_ip_libs selects the IP library to keep from 'hdl_lib_uses_ip'. The include_ip_libs is passed on
through the recursion hierarchy via arg_include_ip_libs to ensure that the from the top level library down all
multiple choice IP libraries in 'hdl_lib_uses_ip' that need to be included are indeed included. The multiple choice IP
libraries in 'hdl_lib_uses_ip' that are not in include_ip_libs are excluded.
Note:
. Only the generic HDL libraries and the technology specific libraries that match self.technologyNames are used.
. The hdl_lib_uses_<build type> key only needs to contain all libraries that are declared at the VHDL LIBRARY
clauses of the source files in this library. This derive_all_use_libs() will recursively find all deeper
level libraries as well.
. Pass on exclude_libs through the recursion hierarchy to ensure that the excluded library and all libraries
that are used by it and not by any other library are excluded as well.
. Only the generic HDL libraries and the technology specific libraries that match self.technologyNames are used,
because the other technology libraries have been removed from self.libs.dicts already at __init__() and from the
library dependency lists in get_used_libs()
"""
# use list() to take local copy, to avoid next that default empty list argument arg_exclude_libs=[] gets disturbed
exclude_libs = list(arg_exclude_libs)
# use list() to take local copy, to avoid next that default empty list argument arg_include_ip_libs=[] gets disturbed
include_ip_libs = list(arg_include_ip_libs)
if lib_name in self.lib_names:
all_use_libs = [lib_name]
lib_dict = self.libs.dicts[self.lib_names.index(lib_name)]
# use recursion to include all used libs
use_libs, exclude_libs = self.get_used_libs(build_type, lib_dict, exclude_libs)
use_libs, include_ip_libs = self.get_used_libs(build_type, lib_dict, include_ip_libs)
for use_lib in use_libs:
if use_lib in self.lib_names:
if use_lib not in all_use_libs:
all_use_libs.append(use_lib)
all_use_libs += self.derive_all_use_libs(build_type, use_lib, exclude_libs)
# use recursion to include all used libs
all_use_libs += self.derive_all_use_libs(build_type, use_lib, include_ip_libs)
# remove all duplicates from the list
return cm.unique(all_use_libs)
else:
sys.exit('Error : Unknown HDL library name')
sys.exit('Error : Unknown HDL library name %s in derive_all_use_libs()' % lib_name)
def derive_lib_order(self, build_type, lib_names=None):
"""Derive the dependency order for all HDL libraries in the fully specified list of lib_names.
Note:
. Only the generic HDL libraries and the technology specific libraries that match self.technologyNames are used.
. The lib_names list must include all used libs, so if necessary first call derive_all_use_libs().
def derive_lib_order(self, build_type, lib_name, lib_names=None):
"""Derive the dependency order for all HDL libraries in lib_names that HDL library lib_name depends on.
"""
if lib_names==None: lib_names=self.lib_names
if lib_names==None:
# At first entry derive the list of all HDL libraries that lib_name depends on
lib_names = self.derive_all_use_libs(build_type, lib_name)
# Derive the order of all HDL libraries that lib_name depends on, start with the order of lib_names
lib_dicts = self.libs.get_dicts('hdl_lib_name', values=lib_names)
# use list() to take local copy to avoid modifying list order of self.lib_names which matches self.libs.dicts list order
lib_order = list(lib_names)
for lib_dict in cm.listify(lib_dicts):
lib_name = lib_dict['hdl_lib_name']
use_libs, exclude_libs = self.get_used_libs(build_type, lib_dict, [])
use_libs, _ = self.get_used_libs('', lib_dict, [])
for use_lib in use_libs:
if use_lib in lib_names:
if lib_order.index(use_lib) > lib_order.index(lib_name):
......@@ -191,7 +248,7 @@ class HdlConfig:
lib_order.insert(lib_order.index(lib_name), use_lib) # move used lib to just before this lib
# use recursion to keep on reordering the lib_order until it is stable
if lib_names != lib_order:
lib_order = self.derive_lib_order(build_type, lib_order)
lib_order = self.derive_lib_order(build_type, lib_name, lib_order)
return lib_order
......@@ -265,8 +322,7 @@ class HdlConfig:
lib_dicts = self.libs.get_dicts('hdl_lib_name', values=lib_names)
for lib_dict in cm.listify(lib_dicts):
lib_name = lib_dict['hdl_lib_name']
use_libs = self.derive_all_use_libs(build_type, lib_name)
lib_order = self.derive_lib_order(build_type, use_libs)
lib_order = self.derive_lib_order(build_type, lib_name)
file_name = lib_name + '_lib_order.txt'
file_path = self.get_lib_build_dirs('sim', lib_dicts=lib_dict)
cm.mkdir(file_path)
......@@ -326,7 +382,7 @@ class HdlConfig:
copy_tree(sourcePathName, destinationPath) # copy directory tree (will create new destinationPath directory)
class Hdl_args:
class HdlParseArgs:
""" Parse command line arguments
"""
def __init__(self, toolsetSelect):
......@@ -359,7 +415,7 @@ if __name__ == '__main__':
mode = 0
# Parse command line arguments
hdl_args = Hdl_args(toolsetSelect=['unb1', 'unb2', 'unb2a'])
hdl_args = HdlParseArgs(toolsetSelect=['unb1', 'unb2', 'unb2a'])
# Read the dictionary info from all HDL tool and library configuration files in the current directory and the sub directories
hdl = HdlConfig(toolRootDir=os.path.expandvars('$RADIOHDL/tools'), libFileName='hdllib.cfg', toolFileName=hdl_args.toolFileName)
......@@ -395,37 +451,33 @@ if __name__ == '__main__':
print ' %-52s :' % lib_name, lib_dict['section_headers']
print ''
print 'Library names = \n', hdl.lib_names
print ''
print 'derive_lib_order for sim :\n', hdl.derive_lib_order('sim')
print 'Removed library names = \n', hdl.removed_lib_names
print ''
print 'derive_lib_order for synth :\n', hdl.derive_lib_order('synth')
print 'Library names = \n', hdl.lib_names
print ''
print 'get_lib_build_dirs for simulation:'
for sim_dir in hdl.get_lib_build_dirs('sim'):
print ' ', sim_dir
for build_dir in hdl.get_lib_build_dirs('sim'):
print ' ', build_dir
print ''
if hdl.libRootDir=='RADIOHDL':
#use_libs = hdl.derive_all_use_libs('sim', 'unb1_minimal')
#use_libs = hdl.derive_all_use_libs('sim', 'dp')
#use_libs = hdl.derive_all_use_libs('sim', 'tech_xaui')
use_libs = hdl.derive_all_use_libs('sim', 'unb1_test_10GbE')
use_libs = hdl.derive_all_use_libs('sim', 'tech_ddr')
print ''
print 'derive_all_use_libs = \n', use_libs
lib_order = hdl.derive_lib_order('sim', use_libs)
print ''
print 'derive_lib_order = \n', lib_order
if hdl.libRootDir=='UNB':
use_libs = hdl.derive_all_use_libs('sim', 'unb_minimal')
use_libs = hdl.derive_all_use_libs('sim', 'dp')
print 'get_lib_build_dirs for synthesis:'
for build_dir in hdl.get_lib_build_dirs('synth'):
print ' ', build_dir
top_lib = 'dp'
top_lib = 'tech_xaui'
if hdl_args.toolset=='unb1': top_lib = 'unb1_test_10GbE'
if hdl_args.toolset=='unb1': top_lib = 'unb1_ddr3'
if hdl_args.toolset=='unb1': top_lib = 'unb1_minimal'
if hdl_args.toolset=='unb2': top_lib = 'unb2_minimal'
if hdl_args.toolset=='unb2a': top_lib = 'unb2a_minimal'
for build_type in ['sim', 'synth']:
print ''
print 'derive_all_use_libs = \n', use_libs
lib_order = hdl.derive_lib_order('sim', use_libs)
print 'derive_all_use_libs for %s of %s = \n' % (build_type, top_lib), hdl.derive_all_use_libs(build_type, top_lib)
print ''
print 'derive_lib_order = \n', lib_order
print 'derive_lib_order for %s of %s = \n' % (build_type, top_lib), hdl.derive_lib_order(build_type, top_lib)
if mode==1:
key = 'build_dir'
......
tools/oneclick/base/quartus_config.py
+ 2
− 3
View file @ 0b67c77b
......@@ -216,8 +216,7 @@ class QuartusConfig(hdl_config.HdlConfig):
fp.write('\n')
fp.write('# All used HDL library *_lib.qip files in order with top level last\n')
use_lib_names = self.derive_all_use_libs('synth', lib_name)
use_lib_order = self.derive_lib_order('synth', use_lib_names)
use_lib_order = self.derive_lib_order('synth', lib_name)
#use_lib_dicts = self.libs.get_dicts('hdl_lib_name', values=use_lib_order) # uses original libs.dicts order, but
use_lib_dicts = self.get_lib_dicts_from_lib_names(lib_names=use_lib_order) # must preserve use_lib_order order to ensure that top level design qip with sdc file is include last in qsf
for lib_dict in cm.listify(use_lib_dicts):
......@@ -229,7 +228,7 @@ class QuartusConfig(hdl_config.HdlConfig):
if __name__ == '__main__':
# Parse command line arguments
hdl_args = hdl_config.Hdl_args(toolsetSelect=['unb1', 'unb2', 'unb2a'])
hdl_args = hdl_config.HdlParseArgs(toolsetSelect=['unb1', 'unb2', 'unb2a'])
# Read the dictionary info from all HDL tool and library configuration files in the current directory and the sub directories
qsyn = QuartusConfig(toolRootDir=os.path.expandvars('$RADIOHDL/tools'), libFileName='hdllib.cfg', toolFileName=hdl_args.toolFileName)
......
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