add mms_dp_bsn_source_v2.vhd

libraries/base/dp/hdllib.cfg

@@ -77,6 +77,7 @@ synth_files =
     src/vhdl/dp_bsn_source_v2.vhd
     src/vhdl/dp_bsn_source_reg.vhd
     src/vhdl/mms_dp_bsn_source.vhd
+    src/vhdl/mms_dp_bsn_source_v2.vhd
     src/vhdl/dp_bsn_scheduler.vhd
     src/vhdl/dp_bsn_scheduler_reg.vhd
     src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -184,6 +185,7 @@ test_bench_files =
     tb/vhdl/tb_dp_bsn_align.vhd
     tb/vhdl/tb_mms_dp_bsn_align.vhd
     tb/vhdl/tb_dp_bsn_monitor.vhd
+    tb/vhdl/tb_dp_bsn_source.vhd
     tb/vhdl/tb_dp_bsn_source_v2.vhd
     tb/vhdl/tb_mms_dp_bsn_source.vhd
     tb/vhdl/tb_mms_dp_bsn_source_v2.vhd

libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose : MMS for dp_bsn_source
+-- Description: See dp_bsn_source.vhd
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+
+ENTITY mms_dp_bsn_source_v2 IS
+  GENERIC (
+    g_cross_clock_domain     : BOOLEAN := TRUE;           -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_block_size             : NATURAL := 256;            -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
+    g_nof_block_per_sync     : NATURAL := 8;              -- 800M/1024 = 781250;
+    g_bsn_w                  : NATURAL := 48
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst            : IN  STD_LOGIC;         -- reset synchronous with mm_clk
+    mm_clk            : IN  STD_LOGIC;         -- memory-mapped bus clock
+    dp_rst            : IN  STD_LOGIC;         -- reset synchronous with st_clk
+    dp_clk            : IN  STD_LOGIC;         -- other clock domain clock
+    dp_pps            : IN  STD_LOGIC := '1';  -- external PPS in captured in dp_clk domain
+    
+    -- Memory-mapped clock domain
+    reg_mosi          : IN  t_mem_mosi;  -- actual ranges defined by c_mm_reg
+    reg_miso          : OUT t_mem_miso;  -- actual ranges defined by c_mm_reg
+    
+    -- Streaming clock domain
+    bs_sosi           : OUT t_dp_sosi
+  );
+END mms_dp_bsn_source_v2;
+
+
+ARCHITECTURE str OF mms_dp_bsn_source_v2 IS
+
+  SIGNAL dp_on              : STD_LOGIC;
+  SIGNAL dp_on_pps          : STD_LOGIC;
+  SIGNAL nof_block_per_sync : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL init_bsn           : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+  
+  SIGNAL i_bs_sosi          : t_dp_sosi;
+
+  SIGNAL dp_on_status       : STD_LOGIC;
+  
+  SIGNAL capture_bsn        : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+BEGIN
+
+  bs_sosi <= i_bs_sosi;
+
+  u_mm_reg : ENTITY work.dp_bsn_source_reg
+  GENERIC MAP (
+    g_cross_clock_domain => g_cross_clock_domain,
+    g_nof_block_per_sync => g_nof_block_per_sync
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+    st_rst                => dp_rst,
+    st_clk                => dp_clk,
+    
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in                => reg_mosi,
+    sla_out               => reg_miso,
+    
+    -- MM registers in st_clk domain
+    st_on                 => dp_on,
+    st_on_pps             => dp_on_pps,
+    st_on_status          => dp_on_status,
+    st_nof_block_per_sync => nof_block_per_sync,
+    st_init_bsn           => init_bsn,
+    st_current_bsn        => capture_bsn
+  );
+  
+  u_bsn_source : ENTITY work.dp_bsn_source_v2
+  GENERIC MAP (
+    g_block_size             => g_block_size,
+    g_nof_block_per_sync     => g_nof_block_per_sync,
+    g_bsn_w                  => g_bsn_w
+  )
+  PORT MAP (
+    rst                => dp_rst,
+    clk                => dp_clk,
+    pps                => dp_pps,
+    -- MM control
+    dp_on              => dp_on,
+    dp_on_pps          => dp_on_pps,
+    dp_on_status       => dp_on_status,
+    init_bsn           => init_bsn,
+    nof_block_per_sync => nof_block_per_sync,
+    -- Streaming
+    src_out            => i_bs_sosi
+  );
+  
+  --capture_bsn <= i_bs_sosi.bsn;                                                  -- capture current BSN
+  --capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1';          -- capture BSN at external PPS
+  capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND i_bs_sosi.sync='1';  -- capture BSN at internal sync
+  
+END str;
+

libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd

@@ -157,7 +157,7 @@ BEGIN
      WAIT;
   END PROCESS;
 
-  u_dut : ENTITY work.mms_dp_bsn_source
+  u_dut : ENTITY work.mms_dp_bsn_source_v2
   GENERIC MAP (
     g_cross_clock_domain => TRUE,          -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
     g_block_size         => c_block_size,