Initklal commit

applications/apertif/designs/apertif_unb1_cor_mesh_ref/hdllib.cfg

+hdl_lib_name = apertif_unb1_cor_mesh_ref
+hdl_library_clause_name = apertif_unb1_cor_mesh_ref_lib
+hdl_lib_uses_synth = common technology mm i2c unb1_board diag eth tech_tse reorder apertif
+hdl_lib_technology = ip_stratixiv
+
+synth_top_level_entity =
+
+synth_files =   
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_cor_mesh_ref/qsys_apertif_unb1_cor_mesh_ref/synthesis/qsys_apertif_unb1_cor_mesh_ref.v
+    src/vhdl/mmm_apertif_unb1_cor_mesh_ref.vhd
+    src/vhdl/node_apertif_unb1_cor_mesh_ref.vhd
+    src/vhdl/apertif_unb1_cor_mesh_ref.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_apertif_unb1_cor_mesh_ref.vhd
+
+modelsim_copy_files = src/hex hex                                                   
+
+quartus_copy_files = quartus/qsys_apertif_unb1_cor_mesh_ref.qsys .
+                     src/hex hex                                                   
+quartus_qsf_files = 
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+    quartus/apertif_unb1_cor_mesh_ref_pins.tcl
+    
+quartus_qip_files =
+    $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_cor_mesh_ref/qsys_apertif_unb1_cor_mesh_ref/synthesis/qsys_apertif_unb1_cor_mesh_ref.qip
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

applications/apertif/designs/apertif_unb1_cor_mesh_ref/mmm.cfg

+mmm_name = apertif_unb1_cor_mesh_ref
+
+board_select = unb1
+
+custom_peripherals = 
+    reg_diag_data_buf_re    1  1
+    ram_diag_data_buf_re    8  7
+    reg_diag_data_buf_im    1  1
+    ram_diag_data_buf_im    8  7
+    reg_diag_bg             1  3
+    ram_diag_bg             8  7
+    reg_diagnostics         1  6 
+    reg_tr_nonbonded        1  4
+    ram_reorder_row_input   1  7
+    ram_reorder_row_mesh    1  8    
+
+input_clks = mm_clk
+    
+synth_master = qsys
+
+vhdl_output_path = src/vhdl/
+