200MHz revision, added exclude channel mech

applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_200MHz.sdc

+###############################################################################
+#
+# Copyright (C) 2018
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Constrain the input I/O path
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+# Constrain the output I/O path
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+
+
+# False path the PPS to DDIO:
+#set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
+
+
+#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
+
+#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
+
+
+
+set_time_format -unit ns -decimal_places 3
+
+create_clock -period 125Mhz [get_ports {ETH_CLK}]
+create_clock -period 200Mhz [get_ports {CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
+create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+#create_clock -period 100MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group {CLK}
+set_clock_groups -asynchronous -group {BCK_REF_CLK}
+set_clock_groups -asynchronous -group {CLK_USR}
+set_clock_groups -asynchronous -group {CLKUSR}
+set_clock_groups -asynchronous -group {SA_CLK}
+set_clock_groups -asynchronous -group {SB_CLK}
+# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
+
+# IOPLL outputs (which have global names defined in the IP qsys settings)
+set_clock_groups -asynchronous -group [get_clocks pll_clk20]
+set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
+set_clock_groups -asynchronous -group [get_clocks pll_clk125]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+
+
+# FPLL outputs
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk3}]
+
+
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
+
+#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
+
+#set_clock_groups -asynchronous \
+#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
+#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+
+
+
+# false paths added for the jesd test design
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
+set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
+set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+
+# Constraint on the SYSREF input pin
+#    Adjust this to account for any board trace difference between SYSREF and REFCLK
+# See page 150: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
+set_input_delay -clock BCK_REF_CLK 0 [get_ports JESD204B_SYSREF]

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd

@@ -488,8 +488,8 @@ BEGIN
   -----------------------------------------------------------------------------
 
   jesd_mm_rst <= mm_rst OR mm_jesd_ctrl_reg(31);
-  QSFP_LED(0) <= mm_jesd_ctrl_reg(12);
-  QSFP_LED(1) <= mm_jesd_ctrl_reg(13);
+  --QSFP_LED(0) <= mm_jesd_ctrl_reg(12);
+  --QSFP_LED(1) <= mm_jesd_ctrl_reg(13);
   gen_jesd_disable : FOR I IN 0 TO c_nof_streams-1 GENERATE
     jesd_disable(i) <= mm_jesd_ctrl_reg(i);
   END GENERATE;
@@ -504,7 +504,7 @@ BEGIN
   PORT MAP(
     -- clocks and resets
     mm_clk                      => mm_clk,           
-    mm_rst                      => jesd_mm_rst,           
+    mm_rst                      => mm_rst,
     dp_clk                      => dp_clk,           
     dp_rst                      => dp_rst,           
 

libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd

@@ -278,15 +278,15 @@ BEGIN
           csr_s                      => OPEN, 
           dev_lane_aligned           => dev_lane_aligned_arr(i),           
           dev_sync_n                 => jesd204b_sync_n_internal_arr(i),
-          jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
+          jesd204_rx_avs_chipselect         => '1',
           jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
           jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
           jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
           jesd204_rx_avs_waitrequest        => jesd204b_miso_arr(i).waitrequest,
           jesd204_rx_avs_write              => jesd204b_mosi_arr(i).wr,
           jesd204_rx_avs_writedata          => jesd204b_mosi_arr(i).wrdata(31 downto 0),
-          jesd204_rx_avs_clk                => jesd204b_avs_clk, --mm_clk,
-          jesd204_rx_avs_rst_n              => rx_avs_rst_n_arr(i), -- Todo: Check if this could use mm_rst,
+          jesd204_rx_avs_clk                => jesd204b_avs_clk,
+          jesd204_rx_avs_rst_n              => rx_avs_rst_n_arr(i),
           jesd204_rx_dlb_data               => (others => '0'), -- debug/loopback testing
           jesd204_rx_dlb_data_valid  => (others => '0'), -- debug/loopback testing
           jesd204_rx_dlb_disperr     => (others => '0'), -- debug/loopback testing
@@ -303,7 +303,7 @@ BEGIN
           rx_digitalreset            => rx_digitalreset_arr(I DOWNTO I),
           rx_islockedtodata          => rx_islockedtodata_arr(I DOWNTO I),
           rx_serial_data             => serial_rx_arr(i downto i),
-          rxlink_clk                 => rxlink_clk,             -- TODO: still not clear if this should be 100MHz or 200MHz (Intel JESD204B-UG p63)
+          rxlink_clk                 => rxlink_clk,
           rxlink_rst_n_reset_n       => rxlink_rst_n_arr(i),    -- Assoc with rxlink_clk (Intel JESD204B-UG p69)
           rxphy_clk                  => OPEN,                   -- Not used in Subclass 0 (Intel JESD204B-UG p63)
           sof                        => OPEN,
@@ -317,7 +317,7 @@ BEGIN
       -----------------------------------------------------------------------------
       u_ip_arria10_e1sg_jesd204b_rx_reset_seq : ip_arria10_e1sg_jesd204b_rx_reset_seq
       PORT MAP (
-        av_address                 => reset_seq_mosi_arr(i).address(7 downto 0), -- in  std_logic_vector(7 downto 0)  := (others => '0'); 
+        av_address                 => reset_seq_mosi_arr(i).address(7 downto 0),
         av_readdata                => reset_seq_miso_arr(i).rddata(31 downto 0),
         av_read                    => reset_seq_mosi_arr(i).rd,
         av_writedata               => reset_seq_mosi_arr(i).wrdata(31 downto 0),
@@ -339,7 +339,6 @@ BEGIN
         reset_out7                 => rxframe_rst_arr(i)
       );
 
-      --rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
       rx_xcvr_ready_in_arr(i) <= '1' when  rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
 
       -- Invert thr active-low resets
@@ -463,8 +462,13 @@ BEGIN
 
   END GENERATE;
 
-  -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
   gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
+      -- option (a)
+      -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will be forced active
+      --jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) when jesd204b_disable_arr(i) = '0' else '0';
+
+      -- option (b)
+      -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
       jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
   END GENERATE;
 

libraries/technology/jesd204b/tech_jesd204b.vhd

@@ -110,7 +110,7 @@ BEGIN
       jesd204b_sysref      => jesd204b_sysref,   
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
-      jesd204b_disable_arr  => jesd204b_disable_arr,
+      jesd204b_disable_arr => jesd204b_disable_arr,
       jesd204b_reset       => jesd204b_reset,
 
       rx_src_out_arr       => rx_sosi_arr,