Added imtegration interval parameters.

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -116,6 +116,9 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_N_clk_per_sync       : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M clock cycles per second
   CONSTANT c_sdp_N_clk_sync_timeout   : NATURAL := c_sdp_f_adc_MHz*10**6 + c_sdp_f_adc_MHz*10**5;  -- 10% margin.
   CONSTANT c_sdp_N_sync_jesd          : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
+  CONSTANT c_sdp_f_sub_Hz             : REAL := REAL(c_sdp_f_adc_MHz * 10**6) / REAL(c_sdp_N_fft);
+  CONSTANT c_sdp_N_int                : NATURAL := c_sdp_f_adc_MHz * 10**6;  -- nof ADC sample periods per 1 s integration interval
+  CONSTANT c_sdp_N_int_sub            : REAL := c_sdp_f_sub_Hz;  -- nof subband sample periods per 1 s integration interval
   CONSTANT c_sdp_A_pn                 : NATURAL := c_sdp_S_pn / c_sdp_N_pol;  -- = 6 dual pol antenna per PN, is 6 signal input pairs
   CONSTANT c_sdp_P_pfb                : NATURAL := c_sdp_S_pn / c_sdp_Q_fft;  -- = 6 PFB units, for 6 signal input pairs
   CONSTANT c_sdp_T_adc                : TIME    := (10**6 / c_sdp_f_adc_MHz) * 1 ps;  -- = 5 ns @ 200MHz