Skip to content
Snippets Groups Projects
Commit 08a1c0e2 authored by Eric Kooistra's avatar Eric Kooistra
Browse files

Ported mac_10g from $UNB to ip_stratixiv_mac_10g.vhd in $RADIOHDL.

parent aa710a58
No related branches found
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
libraries/technology/ip_stratixiv/mac_10gbe/ip_stratixiv_mac_10g.vhd 0 → 100644
+ 175
− 0
View file @ 08a1c0e2
-- megafunction wizard: %Ethernet 10G MAC v11.1%
-- GENERATION: XML
-- ip_stratixiv_mac_10g.vhd
-- Generated using ACDS version 11.1sp2 259 at 2013.04.25.20:38:09
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ip_stratixiv_mac_10g is
port (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
csr_reset_reset_n : in std_logic := '0'; -- csr_reset.reset_n
csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- csr.address
csr_waitrequest : out std_logic; -- .waitrequest
csr_read : in std_logic := '0'; -- .read
csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
csr_write : in std_logic := '0'; -- .write
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
tx_clk_clk : in std_logic := '0'; -- tx_clk.clk
tx_reset_reset_n : in std_logic := '0'; -- tx_reset.reset_n
avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
avalon_st_tx_valid : in std_logic := '0'; -- .valid
avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
avalon_st_tx_ready : out std_logic; -- .ready
avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => '0'); -- .error
avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
xgmii_tx_data : out std_logic_vector(71 downto 0); -- xgmii_tx.data
avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
rx_clk_clk : in std_logic := '0'; -- rx_clk.clk
rx_reset_reset_n : in std_logic := '0'; -- rx_reset.reset_n
xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
avalon_st_rx_startofpacket : out std_logic; -- avalon_st_rx.startofpacket
avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
avalon_st_rx_valid : out std_logic; -- .valid
avalon_st_rx_ready : in std_logic := '0'; -- .ready
avalon_st_rx_data : out std_logic_vector(63 downto 0); -- .data
avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- link_fault_status_xgmii_rx.data
);
end entity ip_stratixiv_mac_10g;
architecture rtl of ip_stratixiv_mac_10g is
component ip_stratixiv_mac_10g_0002 is
port (
csr_clk_clk : in std_logic := 'X'; -- clk
csr_reset_reset_n : in std_logic := 'X'; -- reset_n
csr_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
csr_waitrequest : out std_logic; -- waitrequest
csr_read : in std_logic := 'X'; -- read
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_write : in std_logic := 'X'; -- write
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
tx_clk_clk : in std_logic := 'X'; -- clk
tx_reset_reset_n : in std_logic := 'X'; -- reset_n
avalon_st_tx_startofpacket : in std_logic := 'X'; -- startofpacket
avalon_st_tx_valid : in std_logic := 'X'; -- valid
avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => 'X'); -- data
avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => 'X'); -- empty
avalon_st_tx_ready : out std_logic; -- ready
avalon_st_tx_error : in std_logic_vector(0 downto 0) := (others => 'X'); -- error
avalon_st_tx_endofpacket : in std_logic := 'X'; -- endofpacket
avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => 'X'); -- data
xgmii_tx_data : out std_logic_vector(71 downto 0); -- data
avalon_st_txstatus_valid : out std_logic; -- valid
avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- data
avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- error
rx_clk_clk : in std_logic := 'X'; -- clk
rx_reset_reset_n : in std_logic := 'X'; -- reset_n
xgmii_rx_data : in std_logic_vector(71 downto 0) := (others => 'X'); -- data
avalon_st_rx_startofpacket : out std_logic; -- startofpacket
avalon_st_rx_endofpacket : out std_logic; -- endofpacket
avalon_st_rx_valid : out std_logic; -- valid
avalon_st_rx_ready : in std_logic := 'X'; -- ready
avalon_st_rx_data : out std_logic_vector(63 downto 0); -- data
avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- empty
avalon_st_rx_error : out std_logic_vector(5 downto 0); -- error
avalon_st_rxstatus_valid : out std_logic; -- valid
avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- data
avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- error
link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0) -- data
);
end component ip_stratixiv_mac_10g_0002;
begin
ip_stratixiv_mac_10g_inst : component ip_stratixiv_mac_10g_0002
port map (
csr_clk_clk => csr_clk_clk, -- csr_clk.clk
csr_reset_reset_n => csr_reset_reset_n, -- csr_reset.reset_n
csr_address => csr_address, -- csr.address
csr_waitrequest => csr_waitrequest, -- .waitrequest
csr_read => csr_read, -- .read
csr_readdata => csr_readdata, -- .readdata
csr_write => csr_write, -- .write
csr_writedata => csr_writedata, -- .writedata
tx_clk_clk => tx_clk_clk, -- tx_clk.clk
tx_reset_reset_n => tx_reset_reset_n, -- tx_reset.reset_n
avalon_st_tx_startofpacket => avalon_st_tx_startofpacket, -- avalon_st_tx.startofpacket
avalon_st_tx_valid => avalon_st_tx_valid, -- .valid
avalon_st_tx_data => avalon_st_tx_data, -- .data
avalon_st_tx_empty => avalon_st_tx_empty, -- .empty
avalon_st_tx_ready => avalon_st_tx_ready, -- .ready
avalon_st_tx_error => avalon_st_tx_error, -- .error
avalon_st_tx_endofpacket => avalon_st_tx_endofpacket, -- .endofpacket
avalon_st_pause_data => avalon_st_pause_data, -- avalon_st_pause.data
xgmii_tx_data => xgmii_tx_data, -- xgmii_tx.data
avalon_st_txstatus_valid => avalon_st_txstatus_valid, -- avalon_st_txstatus.valid
avalon_st_txstatus_data => avalon_st_txstatus_data, -- .data
avalon_st_txstatus_error => avalon_st_txstatus_error, -- .error
rx_clk_clk => rx_clk_clk, -- rx_clk.clk
rx_reset_reset_n => rx_reset_reset_n, -- rx_reset.reset_n
xgmii_rx_data => xgmii_rx_data, -- xgmii_rx.data
avalon_st_rx_startofpacket => avalon_st_rx_startofpacket, -- avalon_st_rx.startofpacket
avalon_st_rx_endofpacket => avalon_st_rx_endofpacket, -- .endofpacket
avalon_st_rx_valid => avalon_st_rx_valid, -- .valid
avalon_st_rx_ready => avalon_st_rx_ready, -- .ready
avalon_st_rx_data => avalon_st_rx_data, -- .data
avalon_st_rx_empty => avalon_st_rx_empty, -- .empty
avalon_st_rx_error => avalon_st_rx_error, -- .error
avalon_st_rxstatus_valid => avalon_st_rxstatus_valid, -- avalon_st_rxstatus.valid
avalon_st_rxstatus_data => avalon_st_rxstatus_data, -- .data
avalon_st_rxstatus_error => avalon_st_rxstatus_error, -- .error
link_fault_status_xgmii_rx_data => link_fault_status_xgmii_rx_data -- link_fault_status_xgmii_rx.data
);
end architecture rtl; -- of ip_stratixiv_mac_10g
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_eth_10g_mac" version="11.1" >
-- Retrieval info: <generic name="PREAMBLE_PASSTHROUGH" value="0" />
-- Retrieval info: <generic name="ENABLE_PFC" value="0" />
-- Retrieval info: <generic name="PFC_PRIORITY_NUM" value="8" />
-- Retrieval info: <generic name="DATAPATH_OPTION" value="3" />
-- Retrieval info: <generic name="ENABLE_SUPP_ADDR" value="1" />
-- Retrieval info: <generic name="INSTANTIATE_TX_CRC" value="1" />
-- Retrieval info: <generic name="INSTANTIATE_STATISTICS" value="1" />
-- Retrieval info: <generic name="REGISTER_BASED_STATISTICS" value="0" />
-- Retrieval info: <generic name="DEVICE_FAMILY" value="Stratix IV" />
-- Retrieval info: </instance>
-- IPFS_FILES : ip_stratixiv_mac_10g.vho
-- RELATED_FILES: ip_stratixiv_mac_10g.vhd, ip_stratixiv_mac_10g_0002.v, altera_merlin_master_translator.sv, altera_avalon_mm_bridge.v, altera_eth_packet_underflow_control.v, altera_eth_pad_inserter.v, altera_eth_pkt_backpressure_control.v, altera_eth_pause_beat_conversion.v, altera_eth_pause_controller.v, altera_eth_pause_ctrl_gen.v, altera_eth_pause_gen.v, ip_stratixiv_mac_10g_tx_st_pause_ctrl_error_adapter.v, ip_stratixiv_mac_10g_tx_st_mux_flow_control_user_frame.v, altera_eth_address_inserter.v, altera_eth_crc.v, crc32.v, gf_mult32_kc.v, altera_avalon_st_pipeline_stage.sv, altera_avalon_st_pipeline_base.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_frame_decoder.v, altera_eth_frame_decoder.v, ip_stratixiv_mac_10g_tx_st_error_adapter_stat.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_eth_10gmem_statistics_collector.v, altera_eth_packet_formatter.v, altera_eth_xgmii_termination.v, altera_eth_link_fault_generation.v, altera_avalon_mm_bridge.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_interface_conversion.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_lane_decoder.v, altera_eth_link_fault_detection.v, altera_eth_lane_decoder.v, altera_eth_pkt_backpressure_control.v, ip_stratixiv_mac_10g_rx_st_timing_adapter_frame_status_in.v, altera_avalon_st_splitter.sv, altera_eth_frame_decoder.v, altera_avalon_st_pipeline_stage.sv, altera_avalon_st_pipeline_base.v, altera_eth_crc.v, crc32.v, gf_mult32_kc.v, ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v, ip_stratixiv_mac_10g_rx_timing_adapter_frame_status_out_frame_decoder.v, altera_eth_frame_status_merger.v, altera_eth_crc_pad_rem.v, altera_eth_crc_rem.v, altera_packet_stripper.v, altera_eth_packet_overflow_control.v, altera_avalon_st_delay.sv, ip_stratixiv_mac_10g_rx_st_error_adapter_stat.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_in.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, ip_stratixiv_mac_10g_tx_st_timing_adapter_splitter_status_output.v, altera_avalon_st_delay.sv, altera_eth_10gmem_statistics_collector.v, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_rx.v, altera_avalon_st_splitter.sv, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v, altera_avalon_dc_fifo.v, altera_dcfifo_synchronizer_bundle.v, ip_stratixiv_mac_10g_txrx_timing_adapter_link_fault_status_export.v, ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_rx.v, altera_avalon_dc_fifo.v, altera_dcfifo_synchronizer_bundle.v, ip_stratixiv_mac_10g_rxtx_timing_adapter_pauselen_tx.v, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_master_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_translator.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_master_agent.sv, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, altera_merlin_slave_agent.sv, altera_merlin_burst_uncompressor.sv, altera_avalon_sc_fifo.v, ip_stratixiv_mac_10g_addr_router.sv, ip_stratixiv_mac_10g_id_router.sv, ip_stratixiv_mac_10g_id_router.sv, ip_stratixiv_mac_10g_addr_router_001.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_id_router_002.sv, ip_stratixiv_mac_10g_addr_router_002.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, ip_stratixiv_mac_10g_id_router_010.sv, altera_merlin_traffic_limiter.sv, altera_merlin_traffic_limiter.sv, altera_avalon_st_pipeline_base.v, altera_merlin_traffic_limiter.sv, altera_avalon_st_pipeline_base.v, altera_reset_controller.v, altera_reset_synchronizer.v, altera_reset_controller.v, altera_reset_synchronizer.v, altera_reset_controller.v, altera_reset_synchronizer.v, ip_stratixiv_mac_10g_cmd_xbar_demux.sv, ip_stratixiv_mac_10g_rsp_xbar_demux.sv, ip_stratixiv_mac_10g_rsp_xbar_demux.sv, altera_merlin_arbitrator.sv, ip_stratixiv_mac_10g_rsp_xbar_mux.sv, ip_stratixiv_mac_10g_cmd_xbar_demux_001.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_mux_001.sv, ip_stratixiv_mac_10g_cmd_xbar_demux_002.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_demux_010.sv, ip_stratixiv_mac_10g_rsp_xbar_mux_002.sv, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v, altera_avalon_st_handshake_clock_crosser.v, altera_avalon_st_clock_crosser.v, altera_avalon_st_pipeline_base.v
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment