processed review comments

applications/rdma_demo/libraries/rdma_generator/hdllib.cfg

 hdl_lib_name = rdma_generator
 hdl_library_clause_name = rdma_generator_lib
-hdl_lib_uses_synth = common dp eth axi4 rdma_icrc
+hdl_lib_uses_synth = common dp eth axi4 rdma_icrc_external
 hdl_lib_uses_sim = diag technology tech_tse
 hdl_lib_technology = 
 

applications/rdma_demo/libraries/rdma_generator/src/vhdl/rdma_generator_roce_tester.vhd

@@ -31,7 +31,7 @@
 -- . Avalon is used for all MM interfaces, which can be bridged to AXI4-Lite in
 --   vivado using the AXI AMM Bridge IP.
 
-library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_lib;
+library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_external_lib;
 use IEEE.std_logic_1164.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
@@ -141,7 +141,7 @@ begin
     reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
   );
 
-  u_icrc_append : entity rdma_icrc_lib.append_crc_dp_wrapper
+  u_icrc_append : entity rdma_icrc_external_lib.append_crc_dp_wrapper
   port map (
     dp_clk => st_clk,
     dp_rst => st_rst,

applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd

@@ -18,7 +18,8 @@
 --
 -------------------------------------------------------------------------------
 -- Author: R. vd Walle
--- Purpose: Test bench for eth_tester using high bandwidth generic configuration
+-- Purpose: Test bench for rdma_generator_roce_tester using high bandwidth generic
+-- configuration, e.g. g_nof_octet_output = 64 and g_nof_octet_generate = 64.
 -- Description: Similar to the 1GbE testbench [1] for the eth tester but using generic
 -- values for usage with high bandwidth, e.g. 10 / 100 GbE.
 -- The g_nof_streams >= 1 are tested independently, using g_bg_ctrl_first for
@@ -68,8 +69,11 @@ entity tb_rdma_generator is
     --   nat: mem_low_adrs
     --   nat: mem_high_adrs
     --   nat: bsn_init
-    g_bg_ctrl_first      : t_diag_block_gen_integer := ('1', '1', 500, 3, 200, 0, c_diag_bg_mem_max_adr, 0);  -- for first stream
-    g_bg_ctrl_others     : t_diag_block_gen_integer := ('1', '1', 300, 3, 10, 0, c_diag_bg_mem_max_adr, 0)  -- for other streams
+
+    -- for first stream
+    g_bg_ctrl_first      : t_diag_block_gen_integer := ('1', '1', 500, 3, 200, 0, c_diag_bg_mem_max_adr, 0);
+    -- for other streams
+    g_bg_ctrl_others     : t_diag_block_gen_integer := ('1', '1', 300, 3, 10, 0, c_diag_bg_mem_max_adr, 0)
   );
   port (
     tb_end : out std_logic
@@ -77,7 +81,9 @@ entity tb_rdma_generator is
 end tb_rdma_generator;
 
 architecture tb of tb_rdma_generator is
-  constant c_tb_str                : string := "tb-" & natural'image(g_tb_index) & " : ";  -- use to distinguish logging from tb instances in tb_tb
+  -- use to distinguish logging from tb instances in tb_tb
+  constant c_tb_str                : string := "tb-" & natural'image(g_tb_index) & " : "; 
+
   constant mm_clk_period           : time := 10 ns;  -- 100 MHz
   constant c_nof_st_clk_per_s      : natural := 200 * 10**6;
   constant st_clk_period           : time :=  (10**9 / c_nof_st_clk_per_s) * 1 ns;  -- 5 ns, 200 MHz
@@ -94,6 +100,8 @@ architecture tb of tb_rdma_generator is
   constant c_eth_packet_len_others : natural := func_eth_tester_eth_packet_length(c_bg_block_len_others);
 
   -- Use REAL to avoid NATURAL overflow in bps calculation
+
+
   constant c_bg_nof_bps_first      : real := real(c_bg_block_len_first * c_octet_w) * real(c_nof_st_clk_per_s) / real(c_bg_slot_len_first);
   constant c_bg_nof_bps_others     : real := real(c_bg_block_len_others * c_octet_w) * real(c_nof_st_clk_per_s) / real(c_bg_slot_len_others);
   constant c_bg_nof_bps_total      : real := c_bg_nof_bps_first + real(g_nof_streams - 1) * c_bg_nof_bps_others;
@@ -249,9 +257,13 @@ begin
       -- Set destination MAC/IP/UDP port in tx header, increment udp_dst_port per stream
       -- The MM addresses follow from byte address_offset // 4 in eth.peripheral.yaml
       proc_mem_mm_bus_wr(v_offset + 16#7#, v_udp_dst_port + I, mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
-      proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);  -- use signed to fit 32 b in INTEGER
-      proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);  -- use signed to fit 32 b in INTEGER
-      proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)), mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+      -- use signed to fit 32 b in INTEGER
+      proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr),
+          mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+      proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)),
+          mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi); 
+      proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)),
+          mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
     end loop;
 
     ---------------------------------------------------------------------------
@@ -263,7 +275,8 @@ begin
       proc_mem_mm_bus_wr(I * 2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
 
       -- Prepare the BG
-      proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate) , mm_clk, reg_bg_ctrl_copi);
+      proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate), 
+          mm_clk, reg_bg_ctrl_copi);
       proc_mem_mm_bus_wr(v_offset + 2, bg_ctrl_arr(I).blocks_per_sync,    mm_clk, reg_bg_ctrl_copi);
       proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize,            mm_clk, reg_bg_ctrl_copi);
       proc_mem_mm_bus_wr(v_offset + 4, bg_ctrl_arr(I).mem_low_adrs,       mm_clk, reg_bg_ctrl_copi);
@@ -419,13 +432,18 @@ begin
         -- the ETH data rate < 1 Gbps and no BG block flow control.
         -- Verify, only log when wrong
         if I = 0 then
-          assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
-          assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+          assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report 
+              c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
+          assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report 
+              c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
         else
-          assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
-          assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
+          assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report 
+              c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
+          assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report 
+              c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
         end if;
-        assert tx_mon_latency_arr(I) = c_tx_exp_latency report c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
+        assert tx_mon_latency_arr(I) = c_tx_exp_latency report 
+            c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
 
         -- For short block lengths the Rx latency appears to become less, the
         -- exact Rx latency is therefore hard to predetermine. The actual

applications/rdma_demo/libraries/rdma_icrc/hdllib.cfg → applications/rdma_demo/libraries/rdma_icrc_external/hdllib.cfg

-hdl_lib_name = rdma_icrc
-hdl_library_clause_name = rdma_icrc_lib
+hdl_lib_name = rdma_icrc_external
+hdl_library_clause_name = rdma_icrc_external_lib
 hdl_lib_uses_synth = common dp axi4
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 
+# External library for performing RDMA ICRC calculation
+# Note That most code is VHDL-2008
 synth_files =
-    src/vhdl/wk_lib/PCK_CRC32_D8.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D16.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D32.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D64.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D128.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D256.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D512.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D1024.vhd
-    src/vhdl/wk_lib/PCK_CRC32_D1_reversed.vhd
-    src/vhdl/wk_lib/crc_pkg.vhd
-    src/vhdl/wk_lib/common_types_pkg.vhd
-    src/vhdl/wk_lib/misc_tools_pkg.vhd
-    src/vhdl/wk_lib/AXI4_pkg.vhd
-    src/vhdl/wk_lib/eth_ip_udp_header_prepend_pkg.vhd
-    src/vhdl/wk_lib/lfsr_pkg.vhd
-    src/vhdl/wk_lib/sdp_ram.vhd
-    src/vhdl/wk_lib/pipeline_delay_ram.vhd
-
+    src/vhdl/PCK_CRC32_D8.vhd
+    src/vhdl/PCK_CRC32_D16.vhd
+    src/vhdl/PCK_CRC32_D32.vhd
+    src/vhdl/PCK_CRC32_D64.vhd
+    src/vhdl/PCK_CRC32_D128.vhd
+    src/vhdl/PCK_CRC32_D256.vhd
+    src/vhdl/PCK_CRC32_D512.vhd
+    src/vhdl/PCK_CRC32_D1024.vhd
+    src/vhdl/PCK_CRC32_D1_reversed.vhd
+    src/vhdl/crc_pkg.vhd
+    src/vhdl/common_types_pkg.vhd
+    src/vhdl/misc_tools_pkg.vhd
+    src/vhdl/AXI4_pkg.vhd
+    src/vhdl/eth_ip_udp_header_prepend_pkg.vhd
+    src/vhdl/lfsr_pkg.vhd
+
+    # Not external, wrapper around common_ram_r_w used in pipeline_delay_ram.vhd
+    src/vhdl/sdp_ram.vhd
+
+    src/vhdl/pipeline_delay_ram.vhd
     src/vhdl/bit_width_config_pkg.512b.vhd
     src/vhdl/rdma_pkg.vhd
     src/vhdl/crc_generator.vhd
     src/vhdl/append_crc.vhd
     src/vhdl/append_crc_wrapper.vhd
+
+    # Not external, wrapper around append_crc.vhd to provide DP interfaces.
     src/vhdl/append_crc_dp_wrapper.vhd
 
 test_bench_files = 

applications/rdma_demo/libraries/rdma_icrc/src/vhdl/append_crc_dp_wrapper.vhd → applications/rdma_demo/libraries/rdma_icrc_external/src/vhdl/append_crc_dp_wrapper.vhd

-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
+-------------------------------------------------------------------------------
 --
--- Create Date: 06/27/2023 10:50:24 AM
--- Design Name: 
--- Module Name: append_crc_wrapper - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- Dependencies: 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
-----------------------------------------------------------------------------------
-
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: R. van der Walle
+-- Purpose: Wrapper around append_crc that provides DP interfaces by converting
+-- the AXI4 interfaces using axi4_stream_dp_bridge.
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx leaf cells in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 library axi4_lib, dp_lib;
 use axi4_lib.axi4_stream_pkg.all;
 use dp_lib.dp_stream_pkg.all;