Added remark about related components.

libraries/base/dp/src/vhdl/dp_fifo_info.vhd

@@ -63,6 +63,12 @@
 --   dp_block_gen. This assumes that the DSP does pass on the valid, that the
 --   block size is known and that the first valid at the output corresponds
 --   to a sop.
+-- . These are related components that try to pass on sosi info from begin to
+--   end, without having to pass it on through each step in the sosi data
+--   processing.
+--   - dp_paged_sop_eop_reg
+--   - dp_fifo_info.vhd
+--   - dp_block_gen_valid_arr
 
 LIBRARY IEEE, common_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd

@@ -32,6 +32,12 @@
 --     eop_wr_en <= snk_in.eop & snk_in.eop;
 --   to capture the input at the first wr_en and hold it for output at the
 --   next wr_en.
+-- . These are related components that try to pass on sosi info from begin to
+--   end, without having to pass it on through each step in the sosi data
+--   processing.
+--   - dp_paged_sop_eop_reg
+--   - dp_fifo_info.vhd
+--   - dp_block_gen_valid_arr
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;