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Commit 048ffd68 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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initial IP header set on tr_10GbE

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# synth_files
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_mm.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_ctlr.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy_reg.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio.vhd
set_global_assignment -name VHDL_FILE /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/avs_mdio.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_pkg.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_mm.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_ctlr.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy_reg.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_phy.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/mdio.vhd
set_global_assignment -name VHDL_FILE /home/hiemstra/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/Lofar/mdio/src/vhdl/avs_mdio.vhd
hdl_lib_name = tr_10GbE
hdl_library_clause_name = tr_10GbE_lib
hdl_lib_uses = common dp diag diagnostics tr_xaui eth
hdl_lib_uses = common technology tr_xaui dp diag diagnostics eth
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
......
......@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_memory_lib;
LIBRARY IEEE, common_lib, dp_lib, diag_lib, tr_xaui_lib, technology_lib, tech_memory_lib, tech_transceiver_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -43,6 +43,8 @@ ENTITY tr_10GbE IS
g_lpbk_xgmii : BOOLEAN := FALSE; -- ^^ ^^ ^^
g_lpbk_xaui : BOOLEAN := FALSE; -- g_lpbk_xaui| g_lpbk_xgmii| g_lpbk_sosi|
g_use_hdr_ram : BOOLEAN := FALSE;
g_hdr_ram_init_file : STRING := "UNUSED";
g_hdr_release_at_init : STD_LOGIC := '0'; -- '1' = Release header onto datapath at init
g_word_alignment_padding : BOOLEAN := FALSE
);
PORT (
......@@ -106,7 +108,7 @@ ARCHITECTURE str OF tr_10GbE IS
CONSTANT c_hdr_insert_ram_addr_w : NATURAL := ceil_log2( c_nof_header_words * (c_xgmii_data_w/c_word_w) );
CONSTANT c_hdr_remove_ram_addr_w : NATURAL := ceil_log2( c_nof_header_words * (c_xgmii_data_w/c_word_w) );
CONSTANT c_fifo_margin : NATURAL := 10;
CONSTANT c_fifo_margin : NATURAL := g_pkt_len;
CONSTANT c_word_alignment_padding_nof_bytes : NATURAL := 6; -- 6 Bytes (=48 bits) of padding aligns the 336 bit eth/ip/udp header to a 64b word boundary: 336+48=384 (multiple of 64).
......@@ -245,7 +247,9 @@ BEGIN
g_data_w => c_xgmii_data_w,
g_symbol_w => c_byte_w,
g_hdr_nof_words => c_nof_header_words,
g_internal_bypass => NOT g_use_hdr_ram
g_internal_bypass => NOT g_use_hdr_ram,
g_init_hdr => g_hdr_ram_init_file,
g_dp_on_at_init => g_hdr_release_at_init
)
PORT MAP (
mm_rst => mm_rst,
......@@ -554,7 +558,7 @@ BEGIN
end generate;
u_transceiver: entity work.tech_transceiver_arria10_48
u_transceiver: entity tech_transceiver_lib.tech_transceiver_arria10_48
generic map (
g_nof_channels => g_nof_macs
)
......
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