Explained that use of separate shiftram MM control is ok. Use default record...

Explained that use of separate shiftram MM control is ok. Use default record bs_sosi assignment to nxt_dp_shiftram_src_out_timestamped_arr(i).

boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd

@@ -270,10 +270,13 @@ BEGIN
   -- . dp_shiftram uses DOWNTO range arrays internally vs. TO ranges used here.
   --   func_dp_stream_arr_reverse_range is used to reverse the ranges so
   --   the MM control stream indices are correct.
+  -- . The 4 streams are treated individually by the shiftram. This is fine, 
+  --   because it leaves full control to the LCU via the MM interface.
+  --   For Apertif typically the LCU will write the same delay setting to all
+  --   4 streams and in fact to all 64 streams in the PAF.
+  -- . The written delay setting must be applied synchronously at the sync, this
+  --   is ensured by g_use_sync_in=TRUE and bs_sosi.sync.
   -----------------------------------------------------------------------------
-  -- FIXME: The 4 streams are treated individually by the shiftram. Would be better to 
-  --        consider them as one stream so we are sure they all receive the same 
-  --        delay setting. 
   u_dp_shiftram : ENTITY dp_lib.dp_shiftram
   GENERIC MAP (
     g_nof_streams => g_ai.nof_sp, -- 4 signal paths
@@ -348,12 +351,8 @@ BEGIN
   gen_sosi_ctrl : FOR I IN 0 TO g_ai.nof_sp-1 GENERATE
     p_sosi : PROCESS(dp_shiftram_src_out_arr, bs_sosi)
     BEGIN
-      -- BS sets the sync, bsn[], valid, sop and eop for all signal paths
-      nxt_dp_shiftram_src_out_timestamped_arr(I).sync  <= bs_sosi.sync;
-      nxt_dp_shiftram_src_out_timestamped_arr(I).bsn   <= bs_sosi.bsn;
-      nxt_dp_shiftram_src_out_timestamped_arr(I).valid <= bs_sosi.valid;
-      nxt_dp_shiftram_src_out_timestamped_arr(I).sop   <= bs_sosi.sop;
-      nxt_dp_shiftram_src_out_timestamped_arr(I).eop   <= bs_sosi.eop;
+      -- BS sets the sosi sync, bsn, valid, sop and eop for all signal paths
+      nxt_dp_shiftram_src_out_timestamped_arr(I)       <= bs_sosi;
       nxt_dp_shiftram_src_out_timestamped_arr(I).data  <= dp_shiftram_src_out_arr(I).data;
     END PROCESS;
   END GENERATE;