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Commit 036db1e8 authored by Reinier van der Walle's avatar Reinier van der Walle
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Added DDR4 IP to OpenCL BSP

parent 0577b935
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applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml
+ 12
− 3
View file @ 036db1e8
...@@ -19,9 +19,18 @@ ...@@ -19,9 +19,18 @@
</used_resources> </used_resources>
</device> </device>
<!-- Registers, 32 bit @ 125MHz -->
<global_mem name="REG" max_bandwidth="4000" interleaved_bytes="32">
<interface name="board" port="kernel_register_mem" type="slave" width="256" maxburst="1" address="0x000000000" size="0x000001000" latency_type="fixed"/> <!-- 2 X 8GB DDR4-1600 -->
<!--global_mem name="DDR" max_bandwidth="12800" interleaved_bytes="1024"-->
<global_mem name="DDR" max_bandwidth="12800">
<interface name="board" port="kernel_mem0" type="slave" width="512" maxburst="16" address="0x000000000" size="0x200000000" latency="240"/>
<!--interface name="board" port="kernel_mem1" type="slave" width="576" maxburst="64" address="0x200000000" size="0x200000000" latency="240"/-->
</global_mem>
<!-- Registers, 32 bit @ 100MHz -->
<global_mem name="REG" max_bandwidth="3200" interleaved_bytes="32">
<interface name="board" port="kernel_register_mem" type="slave" width="256" maxburst="1" address="0x200000000" size="0x000001000" latency_type="fixed"/>
</global_mem> </global_mem>
<channels> <channels>
......
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ctrl_unb2_board.tcl
+ 1
− 0
View file @ 036db1e8
...@@ -46,4 +46,5 @@ set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_te ...@@ -46,4 +46,5 @@ set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_te
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense_lib.qip" set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_voltage_sens/tech_fpga_voltage_sens_lib.qip" set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_voltage_sens/tech_fpga_voltage_sens_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/fpga_sense/fpga_sense_lib.qip" set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/fpga_sense/fpga_sense_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_ddr/tech_ddr_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/unb2b_board/unb2b_board_lib.qip" set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/unb2b_board/unb2b_board_lib.qip"
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ddr4.qsys 0 → 100755
+ 3345
− 0
View file @ 036db1e8
This diff is collapsed.
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/hdllib.cfg
+ 2
− 1
View file @ 036db1e8
hdl_lib_name = ta2_unb2b_top hdl_lib_name = ta2_unb2b_top
hdl_library_clause_name = ta2_unb2b_top_lib hdl_library_clause_name = ta2_unb2b_top_lib
hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_40GbE ta2_unb2b_10GbE ta2_unb2b_1GbE_mc ta2_unb2b_jesd204b hdl_lib_uses_synth = common technology dp unb2b_board ta2_unb2b_40GbE ta2_unb2b_10GbE ta2_unb2b_1GbE_mc ta2_unb2b_jesd204b #ta2_unb2b_ddr
hdl_lib_uses_sim = hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip = hdl_lib_include_ip =
...@@ -11,6 +11,7 @@ synth_files = ...@@ -11,6 +11,7 @@ synth_files =
ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.vhd
ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
# ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
top.vhd top.vhd
test_bench_files = test_bench_files =
......
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/board/board_kclk_global.ip 0 → 100644
+ 330
− 0
View file @ 036db1e8
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Altera OpenCL</ipxact:vendor>
<ipxact:library>board_kclk_global</ipxact:library>
<ipxact:name>board_kclk_global</ipxact:name>
<ipxact:version>10.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
<ipxact:name>clk</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>clk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>s</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="clockRate" type="longint">
<ipxact:name>clockRate</ipxact:name>
<ipxact:displayName>Clock rate</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="externallyDriven" type="bit">
<ipxact:name>externallyDriven</ipxact:name>
<ipxact:displayName>Externally driven</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="ptfSchematicName" type="string">
<ipxact:name>ptfSchematicName</ipxact:name>
<ipxact:displayName>PTF schematic name</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>global_clk</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="clock" version="19.2"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.2"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>clk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>g</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:master></ipxact:master>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedDirectClock" type="string">
<ipxact:name>associatedDirectClock</ipxact:name>
<ipxact:displayName>Associated direct clock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="clockRate" type="longint">
<ipxact:name>clockRate</ipxact:name>
<ipxact:displayName>Clock rate</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="clockRateKnown" type="bit">
<ipxact:name>clockRateKnown</ipxact:name>
<ipxact:displayName>Clock rate known</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="externallyDriven" type="bit">
<ipxact:name>externallyDriven</ipxact:name>
<ipxact:displayName>Externally driven</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="ptfSchematicName" type="string">
<ipxact:name>ptfSchematicName</ipxact:name>
<ipxact:displayName>PTF schematic name</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
</ipxact:busInterfaces>
<ipxact:model>
<ipxact:views>
<ipxact:view>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
</ipxact:view>
</ipxact:views>
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:moduleName>global_routing_clk</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
<ipxact:parameters></ipxact:parameters>
</ipxact:componentInstantiation>
</ipxact:instantiations>
<ipxact:ports>
<ipxact:port>
<ipxact:name>s</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors></ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>g</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors></ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
</ipxact:ports>
</ipxact:model>
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Altera OpenCL</ipxact:vendor>
<ipxact:library>board_kclk_global</ipxact:library>
<ipxact:name>global_routing_clk</ipxact:name>
<ipxact:version>10.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="AUTO_CLK_CLOCK_RATE" type="longint">
<ipxact:name>AUTO_CLK_CLOCK_RATE</ipxact:name>
<ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
<ipxact:value>400000000</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="device" type="string">
<ipxact:name>device</ipxact:name>
<ipxact:displayName>Device</ipxact:displayName>
<ipxact:value>10AX115U2F45E1SG</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceFamily" type="string">
<ipxact:name>deviceFamily</ipxact:name>
<ipxact:displayName>Device family</ipxact:displayName>
<ipxact:value>Arria 10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
<ipxact:displayName>Generation Id</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bonusData" type="string">
<ipxact:name>bonusData</ipxact:name>
<ipxact:displayName>bonusData</ipxact:displayName>
<ipxact:value>bonusData
{
element $system
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element board_kclk_global
{
}
}
</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
<ipxact:name>hideFromIPCatalog</ipxact:name>
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
<ipxact:value>&lt;boundaryDefinition&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;s&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;global_clk&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;true&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;g&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedDirectClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;clockRateKnown&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemInfos" type="string">
<ipxact:name>systemInfos</ipxact:name>
<ipxact:displayName>systemInfos</ipxact:displayName>
<ipxact:value>&lt;systemInfosDefinition&gt;
&lt;connPtSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;clk&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;clk&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;CLOCK_RATE&lt;/key&gt;
&lt;value&gt;400000000&lt;/value&gt;
&lt;/entry&gt;
&lt;/suppliedSystemInfos&gt;
&lt;consumedSystemInfos/&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;global_clk&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;global_clk&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos/&gt;
&lt;consumedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;CLOCK_RATE&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;/consumedSystemInfos&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;/connPtSystemInfos&gt;
&lt;/systemInfosDefinition&gt;</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="clk" altera:internal="board_kclk_global.clk" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="s" altera:internal="s"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="global_clk" altera:internal="board_kclk_global.global_clk" altera:type="clock" altera:dir="start">
<altera:port_mapping altera:name="g" altera:internal="g"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</ipxact:vendorExtensions>
</ipxact:component>
\ No newline at end of file
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